From patchwork Wed Aug 6 01:24:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuninori Morimoto X-Patchwork-Id: 4682871 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B1096C0338 for ; Wed, 6 Aug 2014 01:24:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6AA920173 for ; Wed, 6 Aug 2014 01:24:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2727620170 for ; Wed, 6 Aug 2014 01:24:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753925AbaHFBYb (ORCPT ); Tue, 5 Aug 2014 21:24:31 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:33535 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753584AbaHFBYb (ORCPT ); Tue, 5 Aug 2014 21:24:31 -0400 Received: by mail-pa0-f42.google.com with SMTP id lf10so2441320pab.1 for ; Tue, 05 Aug 2014 18:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:message-id:from:subject:user-agent:mime-version:to:cc :in-reply-to:references:content-type; bh=mZ2UNuDbHEXUYyGLFf7pF5iR6ZiPkE1JWSPE/QqLCXM=; b=EjLwbYJsQXXPxS5NE3ORXIW9uJAqmV/gnrK/Ywt1HHFHRzMOocKP7/AszQ/DDTOyVU U+IAFFDbwq6Kk1QBhpzY0su/CBLuK3reY9YVG2ZVi7y1oAf9fgfe68qZuZKlqEk1P8bZ 5rA7PMa++JbhQpsIzg0iistDle5BPxCrzZJDz6tZ9glVviB31zo/1Es+oOgqDMSL3FjT UDWy3nL+yeV1DARxnbwQizXy6ttgDWYNNG4wptBIk9MXHRjpKw0AXroTlYF3QgczIEPd iQeroowGYt+pBdK23nCqCzf8DUF2Z3qydDpJKuPYTYoPtdrozMtCF0l8zBse+vRLRIsN P7VA== X-Received: by 10.70.119.2 with SMTP id kq2mr8158975pdb.66.1407288270966; Tue, 05 Aug 2014 18:24:30 -0700 (PDT) Received: from remon.gmail.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id sk6sm3330426pbc.15.2014.08.05.18.24.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 18:24:30 -0700 (PDT) Date: Tue, 05 Aug 2014 18:24:30 -0700 (PDT) Message-ID: <87zjfijtpv.wl%kuninori.morimoto.gx@gmail.com> From: Kuninori Morimoto Subject: [PATCH 2/3 v2] ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR User-Agent: Wanderlust/2.14.0 Emacs/23.3 Mule/6.0 MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") To: Simon , Mike Turquette Cc: Laurent , Magnus , Linux-SH , Geert Uytterhoeven , Kuninori Morimoto In-Reply-To: <874mxql8eh.wl%kuninori.morimoto.gx@gmail.com> References: <87ppgf1kgv.wl%kuninori.morimoto.gx@gmail.com> <874mxql8eh.wl%kuninori.morimoto.gx@gmail.com> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kuninori Morimoto 9f13ee6f83c52065112d3e396e42e3780911ef53 (ARM: shmobile: r8a7790: add div4 clocks) added r8a7790 DIV4 clock support. But, it is missing "0x0100: x 1/8" division ratio. This patch fixes hidden bug. It is based on R-Car H2 v0.7, R-Car M2 v0.9. Reported-by: Yusuke Goda Signed-off-by: Kuninori Morimoto --- arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 17435c1..126ddaf 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -183,8 +183,8 @@ enum { static struct clk div4_clks[DIV4_NR] = { [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), - [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), - [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT), + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT), }; /* DIV6 clocks */