| Message ID | a911866d220f7b0945e0fb12448e0c1faa3ff346.1697199949.git.ysato@users.sourceforge.jp (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Device Tree support for SH7751 based board | expand |
Hi Sato-san, On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato <ysato@users.sourceforge.jp> wrote: > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) > + > +maintainers: > + - Yoshinori Sato <ysato@users.sourceforge.jp> > + > +description: > + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It > + includes PLLs, and variable ratio dividers. > + > + The CPG may also provide a Clock Domain for SoC devices, in combination with > + the CPG Module Stop (MSTP) Clocks. > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,sh7750-cpg # SH7750 > + - renesas,sh7750s-cpg # SH775S > + - renesas,sh7750r-cpg # SH7750R > + - renesas,sh7751-cpg # SH7751 > + - renesas,sh7751r-cpg # SH7751R > + - const: renesas,sh7750-cpg As there are important differences between the CPG variants, I think it makes sense to drop the "renesas,sh7750-cpg", fallback, like you BTW already did in the example below. Then you can drop the "items", and just keep "enum". > +examples: > + - | > + #include <dt-bindings/clock/sh7750.h> > + cpg: clock-controller@ffc00000 { > + #clock-cells = <1>; > + #power-domain-cells = <0>; > + compatible = "renesas,sh7751r-cpg"; > + clocks = <&xtal>; > + clock-names = "xtal"; > + reg = <0xffc00000 20>, <0xfe0a0000 16>; $ make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb: clock-controller@ffc00000: compatible: ['renesas,sh7751r-cpg'] is too short from schema $id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb: clock-controller@ffc00000: 'reg-names' is a required property from schema $id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# > + }; > -- > 2.39.2 > -- Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file mode 100644 index 000000000000..a640968ed005 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato <ysato@users.sourceforge.jp> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + items: + - enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + - const: renesas,sh7750-cpg + + reg: + maxItems: 2 + + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + + clocks: true + + clock-names: true + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sh7750.h> + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + };
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> --- .../bindings/clock/renesas,sh7750-cpg.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml