From patchwork Wed May 22 22:09:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2603781 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 0F1F0DF215 for ; Wed, 22 May 2013 22:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757440Ab3EVWJp (ORCPT ); Wed, 22 May 2013 18:09:45 -0400 Received: from moutng.kundenserver.de ([212.227.126.187]:59692 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757306Ab3EVWJo (ORCPT ); Wed, 22 May 2013 18:09:44 -0400 Received: from axis700.grange (dslb-094-221-111-159.pools.arcor-ip.net [94.221.111.159]) by mrelayeu.kundenserver.de (node=mrbap2) with ESMTP (Nemesis) id 0Lar3w-1UCrM11mnI-00kjU4; Thu, 23 May 2013 00:09:37 +0200 Received: by axis700.grange (Postfix, from userid 1000) id D1A2E40BB4; Thu, 23 May 2013 00:09:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id CE6B040BB3; Thu, 23 May 2013 00:09:36 +0200 (CEST) Date: Thu, 23 May 2013 00:09:36 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: linux-sh@vger.kernel.org cc: Simon Horman , Magnus Damm Subject: [PATCH 1/2] ARM: shmobile: sh73a0: do not overwrite all div4 clock operations Message-ID: User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 X-Provags-ID: V02:K0:UfQ9CPk+VuXxRmisuX/4ymeqWKQwnCYeDRsrSVPS8kx 5XUS+FA3BfJYOa1dhIGMGSkZmWjEGtVFu63yXEV3xCzdTtaQZ/ 5A0AOu3jt1QOr8Qry2CQA/CYwf9mEFz9DeKbRUQ+RFPJoNEELl cZjAhYebxIOjva00g6nwEG5Yr6yIBAKoTg5HoEHCM1lvdJBvmy SrOkg0oWj6Tgmc25AbJUV7/eQ/lyTKiI48C3H99Y4GPmpWb0ce VMFMhP/Njgn+tj0bJhhfiliQwTJOq9BWSwMqlnf9MT1tamwfmK 10DW1p2+cm2FMFU4Q5KKDbDeq1z7bUpcNEDZuQ1DeZzgbGOhaJ sIsh9aaeOtC9dr1yVnhkdQG3ZfPB0HR2aMUq7bx7TrsHtJN980 kpIXxDn/tSEog== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU frequency" intended to replace some clock operations only for the Z-clock, instead it replaced them for all div4 clocks, since all div4 clocks share the same copy of clock operations. Fix this by using a separate clock operations structure for Z-clock. Signed-off-by: Guennadi Liakhovetski --- Simon, this fixes a commit, currently in "next." Alternatively, it can be merged with the problematic commit, mentioned in the text above. arch/arm/mach-shmobile/clock-sh73a0.c | 28 +++++++++++++++------------- 1 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 711ecf1..8cb6738 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -257,9 +257,8 @@ static struct clk twd_clk = { .ops = &twd_clk_ops, }; -static int (*div4_set_rate)(struct clk *clk, unsigned long rate); -static unsigned long (*div4_recalc)(struct clk *clk); -static long (*div4_round_rate)(struct clk *clk, unsigned long rate); +static struct sh_clk_ops zclk_ops; +static const struct sh_clk_ops *div4_clk_ops; static int zclk_set_rate(struct clk *clk, unsigned long rate) { @@ -277,7 +276,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) /* 1:1 - switch off divider */ __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); /* nullify the divider to prepare for the next time */ - ret = div4_set_rate(clk, rate / 2); + ret = div4_clk_ops->set_rate(clk, rate / 2); if (!ret) ret = frqcr_kick(); if (ret > 0) @@ -292,7 +291,7 @@ static int zclk_set_rate(struct clk *clk, unsigned long rate) * set the divider - call the DIV4 method, it will kick * FRQCRB too */ - ret = div4_set_rate(clk, rate); + ret = div4_clk_ops->set_rate(clk, rate); if (ret < 0) goto esetrate; } @@ -304,7 +303,7 @@ esetrate: static long zclk_round_rate(struct clk *clk, unsigned long rate) { - unsigned long div_freq = div4_round_rate(clk, rate), + unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), parent_freq = clk_get_rate(clk->parent); if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) @@ -319,7 +318,7 @@ static unsigned long zclk_recalc(struct clk *clk) * Must recalculate frequencies in case PLL0 has been changed, even if * the divisor is unused ATM! */ - unsigned long div_freq = div4_recalc(clk); + unsigned long div_freq = div4_clk_ops->recalc(clk); if (__raw_readl(FRQCRB) & (1 << 28)) return div_freq; @@ -329,13 +328,16 @@ static unsigned long zclk_recalc(struct clk *clk) static void zclk_extend(void) { + div4_clk_ops = div4_clks[DIV4_Z].ops; + /* We extend the DIV4 clock with a 1:1 pass-through case */ - div4_set_rate = div4_clks[DIV4_Z].ops->set_rate; - div4_round_rate = div4_clks[DIV4_Z].ops->round_rate; - div4_recalc = div4_clks[DIV4_Z].ops->recalc; - div4_clks[DIV4_Z].ops->set_rate = zclk_set_rate; - div4_clks[DIV4_Z].ops->round_rate = zclk_round_rate; - div4_clks[DIV4_Z].ops->recalc = zclk_recalc; + zclk_ops = *div4_clk_ops; + + zclk_ops.set_rate = zclk_set_rate; + zclk_ops.round_rate = zclk_round_rate; + zclk_ops.recalc = zclk_recalc; + + div4_clks[DIV4_Z].ops = &zclk_ops; } enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,