@@ -356,6 +356,13 @@ config CPU_SUBTYPE_SH7785
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
+config CPU_SUBTYPE_SH7786
+ bool "Support SH7786 processor"
+ select CPU_SH4A
+ select CPU_SHX2
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_SUPPORTS_NUMA
+
config CPU_SUBTYPE_SHX3
bool "Support SH-X3 processor"
select CPU_SH4A
@@ -31,7 +31,7 @@ enum cpu_type {
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
- CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
CPU_SH7723, CPU_SHX3,
/* SH4AL-DSP types */
@@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
+ case 0x4004:
+ boot_cpu_data.type = CPU_SH7786;
+ boot_cpu_data.icache.ways = 4;
+ boot_cpu_data.dcache.ways = 4;
+ boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+ CPU_HAS_LLSC;
+ break;
case 0x3008:
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
@@ -432,6 +432,7 @@ static const char *cpu_name[] = {
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
+ [CPU_SH7786] = "SH7786",
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
@@ -107,6 +107,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case CPU_SH7780:
case CPU_SH7781:
case CPU_SH7785:
+ case CPU_SH7786:
case CPU_SH7723:
case CPU_SHX3:
lmodel = &op_model_sh4a_ops;
L2 cache doesn't support now. This only support main cpu though sh7786 is multi core CPU. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> --- arch/sh/Kconfig | 7 +++++++ arch/sh/include/asm/processor.h | 2 +- arch/sh/kernel/cpu/sh4/probe.c | 7 +++++++ arch/sh/kernel/setup.c | 1 + arch/sh/oprofile/common.c | 1 + 5 files changed, 17 insertions(+), 1 deletions(-)