From patchwork Wed May 13 13:08:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546063 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C184690 for ; Wed, 13 May 2020 13:08:55 +0000 (UTC) Received: by mail.kernel.org (Postfix) id BB7F2206CC; Wed, 13 May 2020 13:08:55 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 880B420673; Wed, 13 May 2020 13:08:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kVMNO2Ns" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 880B420673 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589375335; x=1620911335; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=wEXDFyhD27FZDpCBx83MYF8BSCc7p0QLtEEMqVkQwfk=; b=kVMNO2NsH2oPLucy4doYPWJG+Ohuyj4JXRWb8d5Ib5iM5lYOQkJRGw34 Mz6O9PAEIDhWb3Ld3Ar09UemY3j5CIX95zuEGUQy3CIcDs3uMFucBUS7z PCZviQ42mDfqJwpdGTCb4P0jf4iJiC2Kv6PfmNCMyt/r64wruH2QRLeuT ph/r6dTOLePkOwd6jSGpTNeF9wQQ5bgjqj1Sr/EES7LaxVsSM4oXM/hxW /x9VNAblajw1UjEph8kG3TlZE/WFPXx5ptmiw4OOsGEQ/fEDzzOvB/JMD U9iW7sS7CaNkWh8GPRP5fUC4HzCCU49Q1H8D7iZTkzYoIug0AxggM86S4 Q==; IronPort-SDR: u4GtpcwpQ8MLU6OB9FkxDseViNR3YvoIb2dMRW2aHsvK94tIS3YRC/H1aZ1aJGFh447eHJ6kxm q0M9h2sHr59/QU8HxihFuIrdVG6L6VY1StWHUaXYcFnJ+0gUZ1kYwzulTdKX9mKoyjDNMzGlW1 WRoWOxUtL7Qf/vH9i/84trcmss+PxIw8QdVVYIiN1CrScjMZzqrrZF03S7HzRVRK8cubqsbNZk Up62au2XJDvEMe26Udy40kwR9xIUIxKskgvj+ggSJFtYonedtPRoxzWJsNiom5nY35mxdL2tkf n18= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="79438661" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:08:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:08:57 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:08:52 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 0/5] power: Adding support for Microchip Sparx5 SoC Date: Wed, 13 May 2020 15:08:37 +0200 Message-ID: <20200513130842.24847-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 This is an add-on series to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). It adds reset support for Sparx5, using the ocelot reset driver. It is expected that the DT patches are to be taken directly by the arm-soc maintainers. Lars Povlsen (5): dt-bindings: reset: ocelot: Add Sparx5 support power: reset: ocelot: Add support for Sparx5 dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property power: reset: ocelot: Add support for reset switch on load time arm64: dts: sparx5: Add reset support .../bindings/power/reset/ocelot-reset.txt | 13 ++- MAINTAINERS | 1 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++ drivers/power/reset/Kconfig | 3 +- drivers/power/reset/ocelot-reset.c | 95 ++++++++++++++++--- 5 files changed, 105 insertions(+), 18 deletions(-) --- 2.26.2