From patchwork Wed May 13 14:00:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB35760D for ; Wed, 13 May 2020 14:00:40 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 003CA20659; Wed, 13 May 2020 14:00:42 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9EDEE2064E; Wed, 13 May 2020 14:00:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="zzp7C+lq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9EDEE2064E Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378442; x=1620914442; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=tXc6/mHc2+SLyIE4RWS7EYDLa9x7v+roOjcgud5k/FM=; b=zzp7C+lqGqGduxgM1rJIoaYUZP7pd78lPCAPm8c3FLDMf8IB9jrMTPrM ZcMCovqGFwz4JxCPU+oammSJOro4kCFpOUR5qgl77cYIuceIUaJ56jtrH YbUFoU8oV9LZgkrSof0kl0fgOcgiiCz4tXG69e0rg5yqnXfwHk4vd+Db8 TJUhTgxuXt5S1ynbB0EVG3HRgNNK3Wek0/ksLwc5s4ZqPfBcyLnL/29kq 8YEreZwYvK/NgtIJeFDXhy19SteoDEXhBL325BFEwaSCC5aWjR4gpNHwg wNQYqxbfEufZc5/YoJ9AfUkrJVabJcoLxx9567pFI+3NYvb2ZNxfihKAv w==; IronPort-SDR: ZplCVhn7dt1CCXrvIyaxi9B793BQdV1bKqjSMlGMUb4HA8bM99qF+Wp9bNj3XO9slj7PoV908D cSgPoBCVWra8hvvma+1I7zjC4031JbUOISOcJlRV5rTR6P1RqaK/axH7cdYHpYMqMydiItVldv WjTS+58FzWB/Bn8awju8rUKASA1iVxvQ3TNkgajJhegAVvJ1IcPucq7TgObvHrx9O5lNYOUL/7 5y15H2OMurJBB4nVJKLBtrhaqRC7X8TUDT9bGGGi0kk0GW3kXoMxKgzipt+HyCqRiPuUsa4L5F utg= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="75774839" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:41 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:43 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:39 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , Subject: [PATCH 00/10] spi: Adding support for Microchip Sparx5 SoC Date: Wed, 13 May 2020 16:00:21 +0200 Message-ID: <20200513140031.25633-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 This is an add-on series to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). The series add support for Sparx5 on top of the existing ocelot/jaguar2 spi driver. It spins off the existing support for the MSCC platforms into a separate driver, as adding new platforms from the MSCC/Microchip product lines will further complicate (clutter) the original driver. New YAML dt-bindings are provided for the resulting driver. It is expected that the DT patches are to be taken directly by the arm-soc maintainers. Lars Povlsen (10): spi: dw: Add support for polled operation via no IRQ specified in DT spi: dw: Add support for RX sample delay register spi: dw: Add support for client driver memory operations dt-bindings: spi: Add bindings for spi-dw-mchp spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp dt-bindings: spi: spi-dw-mchp: Add Sparx5 support spi: spi-dw-mchp: Add Sparx5 support arm64: dts: sparx5: Add SPI controller arm64: dts: sparx5: Add spi-nor support arm64: dts: sparx5: Add spi-nand devices .../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++ .../bindings/spi/snps,dw-apb-ssi.txt | 7 +- MAINTAINERS | 2 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++ .../boot/dts/microchip/sparx5_pcb125.dts | 16 + .../boot/dts/microchip/sparx5_pcb134.dts | 22 + .../dts/microchip/sparx5_pcb134_board.dtsi | 9 + .../boot/dts/microchip/sparx5_pcb135.dts | 23 + .../dts/microchip/sparx5_pcb135_board.dtsi | 9 + arch/mips/configs/generic/board-ocelot.config | 2 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++ drivers/spi/spi-dw-mmio.c | 93 ---- drivers/spi/spi-dw.c | 31 +- drivers/spi/spi-dw.h | 4 + 16 files changed, 644 insertions(+), 107 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml create mode 100644 drivers/spi/spi-dw-mchp.c --- 2.26.2