From patchwork Fri Jul 17 09:04:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11669571 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B127A60D for ; Fri, 17 Jul 2020 09:04:36 +0000 (UTC) Received: by mail.kernel.org (Postfix) id A99C2208C7; Fri, 17 Jul 2020 09:04:36 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 642D3207FB; Fri, 17 Jul 2020 09:04:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 642D3207FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: axVjeVKxNWqkN2t0fu/bfdRqNq7SfyGF1m47iwbA7EpHbUp18i/rrt9PBSbcYSiyHKpehYp6e7 eCosYtJKekyg== X-IronPort-AV: E=McAfee;i="6000,8403,9684"; a="129643940" X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="129643940" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 02:04:35 -0700 IronPort-SDR: F67Fa1TCehgIy0lp62zZmEZbdUhBWjDbI/UoAnbdVJ0a2AhLunr2MrXhD3sjlgdPwg6xzZgGhJ fw5nBjSg9pwQ== X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="460785963" Received: from enaessen-mobl1.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.251.86.9]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 02:04:31 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , Daniele Alessandrelli , "Paul J. Murphy" , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v4 0/5] Add initial Keem Bay SoC / Board support Date: Fri, 17 Jul 2020 10:04:09 +0100 Message-Id: <20200717090414.313530-1-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Hi, This patch-set adds initial support for a new Intel Movidius SoC code-named Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This initial patch-set enables only the minimal set of components required to make the Keem Bay EVM board boot into initramfs. Changes from v3 to v4: * Renamed SoC dt-bindings file to intel,keembay.yaml * Dropped clock and power domain dt-binding header files (because currently unused) Changes from v2 to v3: * Split dt-bindings patch into 3 different patches (SoC/board bindings, clock bindings, and power domains bindings). * Added dual license (GPL-2.0-only or BSD-3-Clause) to dt-bindings header files and DTS files. Changes from v1 to v2: * Moved keembay-scmi-mailbox driver to a separate patchset * Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree Regards, Daniele Daniele Alessandrelli (5): arm64: Add config for Keem Bay SoC dt-bindings: arm: Add Keem Bay bindings MAINTAINERS: Add maintainers for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay EVM board .../bindings/arm/intel,keembay.yaml | 19 +++ MAINTAINERS | 8 ++ arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 37 ++++++ arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 ++++++++++++++++++ 6 files changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel,keembay.yaml create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi