From patchwork Thu Jul 30 13:00:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11693007 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 75ABC13B6 for ; Thu, 30 Jul 2020 13:02:33 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 653C6208A9; Thu, 30 Jul 2020 13:02:33 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0B5820842 for ; Thu, 30 Jul 2020 13:02:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="UONJUWqF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0B5820842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pl1-f194.google.com with SMTP id w19so1063155plq.3 for ; Thu, 30 Jul 2020 06:02:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Fr7btDklxJ+wqORQ0drPfvC+MVq8o7T7llSZAP0YnxM=; b=UONJUWqFJJF/32nk1xjITTWvaaIc4XGh0HUHB450gMoWlZxhrNAlNScPWG3j2wZjFG Kn02HBhUtMGKhIaQ2Xo4Tl1pbG+4EEqCfus8DskdV0ZTcvjYXCTepC1QiMP5h9iG8t0M C+aCB3oN/qGI1dVUTzJm2f1UQkikEKzlha8rU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Fr7btDklxJ+wqORQ0drPfvC+MVq8o7T7llSZAP0YnxM=; b=sElAFbQuKJlDvO7tNa21X8Ea6HLX8IU1c8ahH8csrc+ga5ZvTa9JI87BawCtpAfG8Z ytOls4kBdR8bi1FCvr8Vmx1/n45jq/zVhk6bG4vrxgYY+OV4IsIHdAZ3vZlex8WnPpoN Ks+poJAbsCB/MGWCMC8Xwvscz7bewNZCwYPcjDrfB9AfjvXFNyb71rQdLZQqAiNVDng2 AHH93pntYMs0DoDdYMF1MKfrIjn7lU1NbcBK8f2Z7aig9ry3yvbDys9U+9ySCNI28U9i u1uSMUwADjZ1ME40QjH73stzZCDgQrqOw9gP9H9HfBbn9VhRJUjDZFTCHSNEsNkweOho QcvA== X-Gm-Message-State: AOAM5327OQtF46YIBU9yt3nwYe6HCdZY1bdT/AohLHw0+6EWCN1gFyME a7mmsqSkIA0xWxTHUuEyAvMFlXUKm3g= X-Google-Smtp-Source: ABdhPJyl+XPEBp3lsaPYkKSu4oC8Ccqn/pDQcNPkQquOMxwIOVedrKk52WN8G7MjICPSSA+FwIoaTw== X-Received: by 2002:a17:90b:297:: with SMTP id az23mr3150256pjb.135.1596114151676; Thu, 30 Jul 2020 06:02:31 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id b13sm6758704pgd.36.2020.07.30.06.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2020 06:02:30 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@armlinux.org.uk, w@1wt.eu, Daniel Palmer Subject: [RFC PATCH 0/3] ARM: mstar: msc313 intc driver Date: Thu, 30 Jul 2020 22:00:41 +0900 Message-Id: <20200730130044.2037509-1-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 This is the first driver for the MStar/SigmaStar chips. All of the chips so far have two instances of this controller. One instance controls what are called "IRQ" interrupts by the vendor code I have seen. The other instance controls what are called "FIQ" interrupts by the vendor code. Presumably because they can be FIQ interrupts. Right now the FIQ bypass is disabled in the GIC so they operate just the same as the IRQ interrupts. The register layouts are the same for both. The FIQ one needs to have the status bit cleared on EOI. RFC because this is my first interrupt controller driver and I expect to have made a bunch of mistakes. Daniel Palmer (3): dt: bindings: interrupt-controller: Add binding description for msc313-intc ARM: mstar: msc313-intc interrupt controller driver ARM: mstar: Add interrupt controller to base dtsi .../mstar,msc313-intc.yaml | 79 +++++++ MAINTAINERS | 2 + arch/arm/boot/dts/mstar-v7.dtsi | 20 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-msc313-intc.c | 222 ++++++++++++++++++ 5 files changed, 324 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml create mode 100644 drivers/irqchip/irq-msc313-intc.c