From patchwork Mon Aug 24 15:10:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11733373 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E55B138A for ; Mon, 24 Aug 2020 15:10:47 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 77DBD2078D; Mon, 24 Aug 2020 15:10:47 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28DE5207CD for ; Mon, 24 Aug 2020 15:10:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Q7PEO64p" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 28DE5207CD Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1598281847; x=1629817847; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=t4cBW0KJQ9oAF55ARnk4BDNoEvlWUJYtIpys/EI51Sk=; b=Q7PEO64ppqw36HieAO+XNu0C0UWC34DpkTg3r/lQxlORkxKxIvcSp/PC Q0XcA6UmH5/zFFLtHknVqqNu+u4zAEIBAwlRXoNK3e6QlKe8+RCcN70sx SK61EIgOkyHCOn9MxsnyVqzrMcv3q3Dgbd59bFunPxvt6OkRbTQmFoRV8 laB6PfoQo7nI636fQFa2Ckaqe20idSNG32eBa5hB27bNCmdcblzmTy2dW U04m6wypSYM4rjQcfvjoprXkbAMa0Z/QKKZHtKZmdDDubCsEass/ruBNN W80yehxwVNR+P8kiTJAUtgXMDED/HoVcoHTMjOhHh0O/r5rkFfMmW11Jv Q==; IronPort-SDR: CmC1ij+6/53nmSXaamACFN8afuFA/IfnsSnlrU2LnWEc8NDuLI5yZndWLtG05i5hGusMZjmBVR 4qNEhEfNNSVCZ3TT7lRgyeKwsZT18f0b9IH4YMrsX/5hP8tr3Uw39qoJcutJtr9KzXfxjFsFjQ hdXRF7xYun1ohCnkKmGv/6Aod217wafBLHeU7z5mQTPzmvN5Jd99jUSxSvsu4FOBNcmH0AAtNC m2APQ6MARLNgG54zTSGm3s4DrFrGoA1x5n3agrHpj9P5yoCq+a7JRvvjdSnjdIgUk2MfljIjVz 9C0= X-IronPort-AV: E=Sophos;i="5.76,349,1592895600"; d="scan'208";a="92912510" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2020 08:10:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 24 Aug 2020 08:10:10 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 24 Aug 2020 08:10:40 -0700 From: Lars Povlsen List-Id: To: Ulf Hansson , Adrian Hunter , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Date: Mon, 24 Aug 2020 17:10:32 +0200 Message-ID: <20200824151035.31093-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 (This is a resend of an identical patch set, sent at a time where Sparx5 support was not integrated yet. With the Sparx5 clock driver and associated header now in place in the v5.9rc series, the driver is now resubmitted for inclusion). The patch adds eMMC support for Sparx5, by adding a driver for the SoC SDHCI controller, DT configuration and DT binding documentation. Changes in v4: - Disable clock if sdhci_add_host() fails - Remove dev_err if sdhci_add_host() fails Changes in v3: - Add dt-bindings for property "microchip,clock-delay" - Enforce "microchip,clock-delay" valid range in driver - Removed a noisy pr_debug() in sdhci_sparx5_adma_write_desc() Changes in v2: - Changes in driver as per review comments - Drop debug code - Drop sysfs code - use usleep_range() - use mmc_hostname() in pr_debug() - Remove deactivated code - Minor cosmetics Lars Povlsen (3): dt-bindings: mmc: Add Sparx5 SDHCI controller bindings sdhci: sparx5: Add Sparx5 SoC eMMC driver arm64: dts: sparx5: Add Sparx5 eMMC support .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 ++ .../boot/dts/microchip/sparx5_pcb125.dts | 23 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++ drivers/mmc/host/Kconfig | 13 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-sparx5.c | 269 ++++++++++++++++++ 8 files changed, 441 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c --- 2.27.0