From patchwork Thu Feb 27 18:22:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D57CA14D5 for ; Thu, 27 Feb 2020 18:22:38 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABED7246A6 for ; Thu, 27 Feb 2020 18:22:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="AHNJraCY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ABED7246A6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1488+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id SLXjYY1556264xljl58a9f3L; Thu, 27 Feb 2020 10:22:38 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.147.1582827758006004530 for ; Thu, 27 Feb 2020 10:22:38 -0800 X-Received: by mail.kernel.org (Postfix) id CBAC2246B7; Thu, 27 Feb 2020 18:22:37 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 8DFA7246AE; Thu, 27 Feb 2020 18:22:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8DFA7246AE X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5816C1FB; Thu, 27 Feb 2020 10:22:37 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC6113F73B; Thu, 27 Feb 2020 10:22:35 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema Date: Thu, 27 Feb 2020 18:22:06 +0000 Message-Id: <20200227182210.89512-10-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: NEZ0xsjlqtT49ZVcnQzUTxbkx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827758; bh=sHXL7WLU+uuCbD1A93sJ7YPdHV1mxYbTxLvxUcVzJ2Y=; h=Cc:Date:From:Reply-To:Subject:To; b=AHNJraCYgHg9dvWlK/h5cZovyy+iGIwYy4Ihraw+KzSYQTnb43n12QQA5XsXdZ4WKNw RyfFC0U4zGyV4my6ABAGcWE/CtvsaHxRj3nofNcrDnRVTdVz7ScOAbPSW2Q0bCoKfqE2Z 1nGvqV8funV/IMQvr+S3SUxIcMYh1ztsqrE= Convert the L2-ECC controller binding to DT schema format using json-schema. This is indented to be just used for error reporting. Signed-off-by: Andre Przywara --- .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 ------- .../bindings/arm/calxeda/l2ecc.yaml | 43 +++++++++++++++++++ 2 files changed, 43 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 000000000000..5481dd7216ba --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + description: | + Should be single bit error interrupt, then double bit error interrupt. + minItems: 2 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + };