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[1/6] dt-bindings: Add Baikal-T1 AXI-bus EHB dts bindings file

Message ID 20200306130732.7E27C8030705@mail.baikalelectronics.ru (mailing list archive)
State Changes Requested
Headers show
Series [1/6] dt-bindings: Add Baikal-T1 AXI-bus EHB dts bindings file | expand

Commit Message

Serge Semin March 6, 2020, 1:07 p.m. UTC
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

This is a specific block embedded into the Baikal-T1 SoC, which is
dedicated to detect AXI-bus protocol errors. So the dts node just
needs to have the "be,bt1-axi-ehb" compatible string, MMIO registers
and interrupts properties declared.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: soc@kernel.org
---
 .../soc/baikal-t1/be,bt1-axi-ehb.yaml         | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-axi-ehb.yaml
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-axi-ehb.yaml b/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-axi-ehb.yaml
new file mode 100644
index 000000000000..f0deeb8f261c
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/baikal-t1/be,bt1-axi-ehb.yaml
@@ -0,0 +1,52 @@ 
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2019 - 2020 BAIKAL ELECTRONICS, JSC
+#
+# Baikal-T1 AXI-bus Errors Handler Block Device Tree Bindings.
+#
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/baikal-t1/be,bt1-axi-ehb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 AXI-bus Errors Handler Block
+
+maintainers:
+  - Serge Semin <fancer.lancer@gmail.com>
+
+description: |
+  AXI3-bus is the main communication bus connecting all high-speed peripheral
+  IP-cores with RAM controller and with MIPS P5600 cores. Traffic arbitration
+  is done by means of Main Interconnect routing IO request from one block to
+  another. In case of any protocol error, device not responding an IRQ is
+  raised and a faulty situation is reported to the AXI EHB described by this
+  bindings.
+
+properties:
+  compatible:
+    const: be,bt1-axi-ehb
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+    axi_ehb: ehb@1F04D110 {
+      compatible = "be,bt1-axi-ehb";
+      reg = <0x1F04D110 0x008>;
+
+      interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...