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+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2019 - 2020 BAIKAL ELECTRONICS, JSC
+#
+# Baikal-T1 AXI-bus Errors Handler Block Device Tree Bindings.
+#
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/baikal-t1/be,bt1-axi-ehb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 AXI-bus Errors Handler Block
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description: |
+ AXI3-bus is the main communication bus connecting all high-speed peripheral
+ IP-cores with RAM controller and with MIPS P5600 cores. Traffic arbitration
+ is done by means of Main Interconnect routing IO request from one block to
+ another. In case of any protocol error, device not responding an IRQ is
+ raised and a faulty situation is reported to the AXI EHB described by this
+ bindings.
+
+properties:
+ compatible:
+ const: be,bt1-axi-ehb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+ axi_ehb: ehb@1F04D110 {
+ compatible = "be,bt1-axi-ehb";
+ reg = <0x1F04D110 0x008>;
+
+ interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...