From patchwork Fri Mar 27 12:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: afzal mohammed X-Patchwork-Id: 11462353 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF89092A for ; Fri, 27 Mar 2020 12:44:59 +0000 (UTC) Received: by mail.kernel.org (Postfix) id B95102082E; Fri, 27 Mar 2020 12:44:59 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 961EF206F2; Fri, 27 Mar 2020 12:44:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cJj+HvEY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 961EF206F2 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=afzal.mohd.ma@gmail.com Received: by mail-pg1-f195.google.com with SMTP id u12so4512586pgb.10; Fri, 27 Mar 2020 05:44:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+k9FpHI6R329k1p5n2ZmxLrGGeywgn+d1U7fGz/e9fs=; b=cJj+HvEYUrch4yUgmLxsQfZstI1JxA0pQDazHNg6IMMsqsjdMjKwmzWoVuCAdMQ2ua EERQg4cDrroRlSqfqACd0CcPBpWMjhlGDMIh2nmjzF6Tr8jcXlT6vvrVuPKFDZGplUui 6VuoAq+7SvMyaKGfd4x36kLvjEhcQFWvsg8ctmPt669FtdT7mglaMQlhJ28EJqweoe0N 36wuQErl0fLfSy2jtG4q2CXGRFRaKlbvmDk3eTxK7XHh7138+I21f2PDMFhymIxrgGXG 0NzesrfPdwA/ykaTatv5zddtQzq5Y1HbMI9OJXfHg4mO1SoI7kMAGQ9ozclney7LWjed 0Jeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+k9FpHI6R329k1p5n2ZmxLrGGeywgn+d1U7fGz/e9fs=; b=EanuYFDQ0iiNH3c3D0EFox2eb6mwv+jQrim1+0TvFteH9m71vqgaM58MzAkfG+hrNb Xz+dx2V+RCnG9GHhUWAelsPPulZthCv4ioZl2/YGFuoie4/03U3LWDd2E8Y03QEWeLeT 8Yaxxj4F4nA0/KmvtAsO64EOASPsLRh4vOK8ZGEot54h1bzPWDzxbRyWdRzg7TeHd3vo +plaZ68TlPDPZTL3X/Mo7Y5U7ez8gBSDlnO1sBQI9DJD1XzuKvpsFuCjnKAT0gVlZGT8 /kCBdnt0CjnOxLD/b1B1Cts5t0ZIfja8dWl3wt0bKSDlN8729FKl9SwREqO9EwW8Ia30 8M9Q== X-Gm-Message-State: ANhLgQ2HbhcRmH3jQ9NZuVKMKL+Xvv7i5LvHiiIFi5/HSP7ERQzn+JTE bj0Hbtg0DHS6EnX++XGNb08= X-Google-Smtp-Source: ADFU+vt4ULTKYB4EI+sbHTJ5JUWGsxXrQ+wP+sgamWxYG48SKpaR8sUaOWRqDMbtt4LvgaR5hQ6/ig== X-Received: by 2002:a65:53c9:: with SMTP id z9mr12309655pgr.405.1585313099156; Fri, 27 Mar 2020 05:44:59 -0700 (PDT) Received: from localhost.localdomain ([49.207.51.33]) by smtp.gmail.com with ESMTPSA id e9sm4085390pfl.179.2020.03.27.05.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2020 05:44:58 -0700 (PDT) From: afzal mohammed List-Id: To: Arnd Bergmann , SoC Team Cc: afzal mohammed , Thomas Gleixner , Tony Lindgren , Alexander Sverdlin , =?utf-8?q?Krzysztof_Ha?= =?utf-8?q?=C5=82asa?= , Viresh Kumar , Lubomir Rintel , Gregory CLEMENT , Hartley Sweeten , Viresh Kumar , Shiraz Hashim , Andrew Lunn , Jason Cooper , Sebastian Hesselbarth , Russell King , Linux ARM , "linux-kernel@vger.kernel.org" , arm-soc , Olof Johansson Subject: [PATCH v4 5/5] ARM: iop32x: replace setup_irq() by request_irq() Date: Fri, 27 Mar 2020 18:14:51 +0530 Message-Id: <20200327124451.4298-1-afzal.mohd.ma@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: References: request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed --- v4: * No change v3: * Split out from series, also split out from ARM patch to subarch level as Thomas suggested to take it thr' respective maintainers * Modify string displayed in case of error as suggested by Thomas * Re-arrange code as required to improve readability * Remove irrelevant parts from commit message & improve v2: * Replace pr_err("request_irq() on %s failed" by pr_err("%s: request_irq() failed" * Commit message massage arch/arm/mach-iop32x/time.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c index 18a4df5c1baa..ae533b66fefd 100644 --- a/arch/arm/mach-iop32x/time.c +++ b/arch/arm/mach-iop32x/time.c @@ -137,13 +137,6 @@ iop_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction iop_timer_irq = { - .name = "IOP Timer Tick", - .handler = iop_timer_interrupt, - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .dev_id = &iop_clockevent, -}; - static unsigned long iop_tick_rate; unsigned long get_iop_tick_rate(void) { @@ -154,6 +147,7 @@ EXPORT_SYMBOL(get_iop_tick_rate); void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; + int irq = IRQ_IOP32X_TIMER0; sched_clock_register(iop_read_sched_clock, 32, tick_rate); @@ -168,7 +162,9 @@ void __init iop_init_time(unsigned long tick_rate) */ write_tmr0(timer_ctl & ~IOP_TMR_EN); write_tisr(1); - setup_irq(IRQ_IOP32X_TIMER0, &iop_timer_irq); + if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, + "IOP Timer Tick", &iop_clockevent)) + pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq); iop_clockevent.cpumask = cpumask_of(0); clockevents_config_and_register(&iop_clockevent, tick_rate, 0xf, 0xfffffffe);