[v2,1/4] dt-bindings: bus: Add Baikal-T1 AXI-bus binding

Commit Message

Serge Semin May 7, 2020, 10:41 p.m. UTC

AXI3-bus is the main communication bus connecting all high-speed
peripheral IP-cores with RAM controller and with MIPS P5600 cores on
Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect
and Errors Handler Block synthesized on top of it, which are
responsible for the AXI-bus traffic arbitration and errors reporting
upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible
with "be,bt1-axi" and "simple-bus" drivers, should have reg property with
AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1
System Controller, IRQ line declared, AXI Interconnect reference clock and
reset line.

Signed-off-by: Serge Semin <[e-mail]>
Cc: Alexey Malahov <[e-mail]>
Cc: Paul Burton <[e-mail]>
Cc: Ralf Baechle <[e-mail]>
Cc: Tony Lindgren <[e-mail]>
Cc: Tero Kristo <[e-mail]>
Cc: Manivannan Sadhasivam <[e-mail]>
Cc: Jeffrey Hugo <[e-mail]>
Cc: Linus Walleij <[e-mail]>
Cc: Olof Johansson <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]

---

Rob, I had to remove your Reviewed-by tag, since new changes had been
introduced.

Changelog v2:
- Move driver to the bus subsystem.
- Use dual GPL/BSD license.
- Use single lined copyright header.
- Lowercase the unit-address.
- Convert a simple EHB block binding to the Baikal-T1 AXI-bus one with
  interconnect capabilities support.
- Replace "additionalProperties: false" property with
  "unevaluatedProperties: false".
- Add AXI reference clock and reset support.
- Add syscon phandle reference to the Baikal-T1 System Controller node.
---
 .../bindings/bus/baikal,bt1-axi.yaml          | 95 +++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml

Comments

Rob Herring (Arm) May 15, 2020, 3:13 a.m. UTC | #1

On Fri, 8 May 2020 01:41:13 +0300, Serge Semin wrote:
> AXI3-bus is the main communication bus connecting all high-speed
> peripheral IP-cores with RAM controller and with MIPS P5600 cores on
> Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect
> and Errors Handler Block synthesized on top of it, which are
> responsible for the AXI-bus traffic arbitration and errors reporting
> upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible
> with "be,bt1-axi" and "simple-bus" drivers, should have reg property with
> AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1
> System Controller, IRQ line declared, AXI Interconnect reference clock and
> reset line.
> 
> Signed-off-by: Serge Semin <[e-mail]>
> Cc: Alexey Malahov <[e-mail]>
> Cc: Paul Burton <[e-mail]>
> Cc: Ralf Baechle <[e-mail]>
> Cc: Tony Lindgren <[e-mail]>
> Cc: Tero Kristo <[e-mail]>
> Cc: Manivannan Sadhasivam <[e-mail]>
> Cc: Jeffrey Hugo <[e-mail]>
> Cc: Linus Walleij <[e-mail]>
> Cc: Olof Johansson <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> 
> ---
> 
> Rob, I had to remove your Reviewed-by tag, since new changes had been
> introduced.
> 
> Changelog v2:
> - Move driver to the bus subsystem.
> - Use dual GPL/BSD license.
> - Use single lined copyright header.
> - Lowercase the unit-address.
> - Convert a simple EHB block binding to the Baikal-T1 AXI-bus one with
>   interconnect capabilities support.
> - Replace "additionalProperties: false" property with
>   "unevaluatedProperties: false".
> - Add AXI reference clock and reset support.
> - Add syscon phandle reference to the Baikal-T1 System Controller node.
> ---
>  .../bindings/bus/baikal,bt1-axi.yaml          | 95 +++++++++++++++++++
>  1 file changed, 95 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml
> 

Reviewed-by: Rob Herring <[e-mail]>

Patch

diff --git a/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml
new file mode 100644
index 000000000000..082ab5c3b4f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml
@@ -0,0 +1,95 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 AXI-bus
+
+maintainers:
+  - Serge Semin <[e-mail]>
+
+description: |
+  AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
+  high-speed peripheral IP-cores with RAM controller and with MIPS P5600
+  cores. Traffic arbitration is done by means of DW AXI Interconnect (so
+  called AXI Main Interconnect) routing IO requests from one block to
+  another: from CPU to SoC peripherals and between some SoC peripherals
+  (mostly between peripheral devices and RAM, but also between DMA and
+  some peripherals). In case of any protocol error, device not responding
+  an IRQ is raised and a faulty situation is reported to the AXI EHB
+  (Errors Handler Block) embedded on top of the DW AXI Interconnect and
+  accessible by means of the Baikal-T1 System Controller.
+
+allOf:
+ - $ref: /schemas/simple-bus.yaml#
+
+properties:
+  compatible:
+    contains:
+      const: baikal,bt1-axi
+
+  reg:
+    maxItems: 1
+
+  '#interconnect-cells':
+    const: 1
+
+  syscon:
+    $ref: /schemas/types.yaml#definitions/phandle
+    description: Phandle to the Baikal-T1 System Controller DT node
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Main Interconnect uplink reference clock
+
+  clock-names:
+    items:
+      - const: aclk
+
+  resets:
+    items:
+      - description: Main Interconnect reset line
+
+  reset-names:
+    items:
+      - const: arst
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - syscon
+  - interrupts
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+    bus@1f05a000 {
+      compatible = "baikal,bt1-axi", "simple-bus";
+      reg = <0 0x1f05a000 0 0x1000>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+      #interconnect-cells = <1>;
+
+      syscon = <&syscon>;
+
+      ranges;
+
+      interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
+
+      clocks = <&ccu_axi 0>;
+      clock-names = "aclk";
+
+      resets = <&ccu_axi 0>;
+      reset-names = "arst";
+    };
+...