From patchwork Thu May 7 23:07:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11535067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7686B1862 for ; Thu, 7 May 2020 23:07:19 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6E240215A4; Thu, 7 May 2020 23:07:19 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail.baikalelectronics.ru (mail.baikalelectronics.com [87.245.175.226]) by mail.kernel.org (Postfix) with ESMTP id 07554208D6; Thu, 7 May 2020 23:07:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 07554208D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baikalelectronics.ru Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Sergey.Semin@baikalelectronics.ru Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 51BF4803087C; Thu, 7 May 2020 23:07:18 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RgeR1JaAaddZ; Fri, 8 May 2020 02:07:17 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Greg Kroah-Hartman , Arnd Bergmann , Rob Herring List-Id: CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Olof Johansson , Boris Brezillon , Paul Cercueil , Thomas Gleixner , Masahiro Yamada , , , , Subject: [PATCH v2 1/2] dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding Date: Fri, 8 May 2020 02:07:03 +0300 Message-ID: <20200507230705.6468-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200507230705.6468-1-Sergey.Semin@baikalelectronics.ru> References: <20200306130731.938808030702@mail.baikalelectronics.ru> <20200507230705.6468-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) There is a single register provided by the SoC system controller, which can be used to tune the L2-cache RAM up. It only provides a way to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" compatible string the device node can be optionally equipped with the properties of Tag/Data/WS latencies. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Paul Burton Cc: Ralf Baechle Cc: Olof Johansson Cc: Boris Brezillon Cc: Paul Cercueil Cc: Thomas Gleixner Cc: Masahiro Yamada Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org --- Changelog v2: - Move driver to the memory subsystem. - Use dual GPL/BSD license. - Use single lined copyright header. - Move "allOf" restrictions to the root level of the properties. - Discard syscon compatible string and reg property. - The DT node is supposed to be a child of the Baikal-T1 system controller node. --- .../memory-controllers/baikal,bt1-l2-ctl.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml new file mode 100644 index 000000000000..263f0cdab4e6 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin + +description: | + By means of the System Controller Baikal-T1 SoC exposes a few settings to + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 + L2-cache controller block is responsible for the tuning. Its DT node is + supposed to be a child of the system controller. + +properties: + compatible: + const: baikal,bt1-l2-ctl + + baikal,l2-ws-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Way-select RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-tag-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Tag RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-data-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Data RAM accesses + default: 1 + minimum: 0 + maximum: 3 + +additionalProperties: false + +required: + - compatible + +examples: + - | + l2_ctl { + compatible = "baikal,bt1-l2-ctl"; + + baikal,l2-ws-latency = <0>; + baikal,l2-tag-latency = <0>; + baikal,l2-data-latency = <1>; + }; +...