From patchwork Wed May 13 12:55:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11545989 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63D0490 for ; Wed, 13 May 2020 12:56:47 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 5D38E206E5; Wed, 13 May 2020 12:56:47 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C2E4206D6; Wed, 13 May 2020 12:56:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="IU4HbcgR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C2E4206D6 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374607; x=1620910607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=poBPrhT3w6QbThTNX7WMhvl6ITRtWZafa6qFqSWWJSM=; b=IU4HbcgRMZG62kCe2iMT51BZ4gViXsELRZ/N6aQNtHzkrzBcpsS+6Ese oDyQ4oxZ6pRWvUBKlg/mf46ox2NwMJ5xotqmIvo3sPyH3Vzyks01POxgL FMLdRNkIQagDDNzKp/sRB5EhjAIFFyW6B7p1+uLnoiqQNtckiWfspRtEX eUGwn2U62ctQTz36yqpGmqujVNA7EfQjPk/4+xuwFDA8c40ZViZ/hXXGC CYPfWS8FaGHQAvXaB4VV3J+LFFQfAhWwEA1acqyNGgCAH8mpHs55/75XK 0ctAYVGKZJsFdRSxXYBDBrBiEaghGtH9PXbs7SxLunqjeI59NXZoSq5oN Q==; IronPort-SDR: xxJdrEOxoKFUoLTD14Tc43OvYgZ/knJ6/cbfPW9+CoTHjCaaQ1u/jmYup6A6CbZQhwERynlnod rFRLF3M/WkpD1TVTYVAN1fmXQV9PmBKBpdq21AnRDX3Htw4lER5Hn6WV0fZ3Q+Z5l/HVaEko8p DE3WRmiUUiLPbP3U1bNAyP2RpFCyQlU7/Vwwl2No0MeKdcrk8QFbonZJpZzCpkVPeGL0+z01xE s/CVAdnli96L3/nH5bHtKt61tiSbkEh+u8NbFYaWRLA9pYgSkO3cTnj7eVdZV4Lvewn6indXai sFM= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76494614" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:48 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:42 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij , Rob Herring CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC Date: Wed, 13 May 2020 14:55:23 +0200 Message-ID: <20200513125532.24585-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds the main Sparx5 SoC DT documentation file, with information abut the supported board types. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml new file mode 100644 index 0000000000000..83b36d1217988 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Boards Device Tree Bindings + +maintainers: + - Lars Povlsen + +description: |+ + The Microchip Sparx5 SoC is a ARMv8-based used in a family of + gigabit TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of switching + features such as advanced TCAM-based VLAN and QoS processing + enabling delivery of differentiated services, and security through + TCAM-based frame processing using versatile content aware processor + (VCAP) + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The Sparx5 pcb125 board is a modular board, + which has both spi-nor and eMMC storage. The modular design + allows for connection of different network ports. + items: + - const: microchip,sparx5-pcb125 + - const: microchip,sparx5 + + - description: The Sparx5 pcb134 is a pizzabox form factor + gigabit switch with 20 SFP ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb134 + - const: microchip,sparx5 + + - description: The Sparx5 pcb135 is a pizzabox form factor + gigabit switch with 48+4 Cu ports. It features spi-nor and + either spi-nand or eMMC storage (mount option). + items: + - const: microchip,sparx5-pcb135 + - const: microchip,sparx5 + + axi@600000000: + type: object + description: the root node in the Sparx5 platforms must contain + an axi bus child node. They are always at physical address + 0x600000000 in all the Sparx5 variants. + properties: + compatible: + items: + - const: simple-bus + reg: + maxItems: 1 + + required: + - compatible + - reg + +patternProperties: + "^syscon@[0-9a-f]+$": + description: All Sparx5 boards must provide a system controller, + typically under the axi bus node. It contain reset registers and + other system control. + type: object + properties: + compatible: + items: + - const: microchip,sparx5-cpu-syscon + - const: syscon + reg: + maxItems: 1 + + required: + - compatible + - reg + +required: + - compatible + - axi@600000000 + - syscon@600000000 + +...