From patchwork Wed May 13 14:00:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546441 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B772660D for ; Wed, 13 May 2020 14:01:01 +0000 (UTC) Received: by mail.kernel.org (Postfix) id D156920690; Wed, 13 May 2020 14:01:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 906DE2065D; Wed, 13 May 2020 14:01:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="LeXTpgmx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 906DE2065D Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378463; x=1620914463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iauAWz+CB287sxl5gww1bSL60uZ1IZfFjbf+2bfJDKU=; b=LeXTpgmxV2+eLAZpID1sT/zKjJ03r5y68WTlf8NSgnyUcpn5gPmokxvy Di80hukVMiGjv5N2eOektnDH3IG0O6LL1oAyFvHaMZAOu1dgx8ZXfoqpp aOa63uAo1ZIujDIx+EL7TOn8x7rjAEt+FXlqX60Cy+EsqafRyRXKq1wbJ ljOxP3yFCPLObU3fCBqe0T/dulpw4kSsSgJYB6T0agGTg719vbk60FcZ4 CnDNnn+XJOL5nuAYcpx97RSXuirElgS2w150HixCl3uRAQimWLE1DrfQn 2EDbPgIfAsNLsrPCZQqI0QRsqVpB9iBofRq/gDNNIlSZ3pz2bz0HwEyot Q==; IronPort-SDR: rJGSY8q8PbCBR7XcB8/siK/Ft2wQh8SFJgTIYblb9ci/I5wfzXdWBC78Jm/Ve7XQKMhDlIbST9 PD7KOxcdgKauy9aexCg2LsfVU5x6IQA8pvNlIzcHBFDY39UQitL9AMbrHfagYhu8MzJWKtoRcq SsVJTwAy13eWseriiCmCbYjFl5SHrWYlKKIiIXhtq35zn6kF9zF9XX3lQZ5J8FDKchWx2UiXur IeFUqBeNMTvYXKvBBeeLIoyLc4qomECTkTOVpg2xL03Ya+WaZH8ONXc2xAgLFcikFQNIvHnfCh wNA= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="73314076" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:01:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:01 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:59 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Date: Wed, 13 May 2020 16:00:30 +0200 Message-ID: <20200513140031.25633-10-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add spi-nor device nodes to the Sparx5 reference boards. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++-- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 9 +++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index daa216978887d..330fd8b096d4c 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -155,8 +155,9 @@ spi0: spi@600104000 { reg-io-width = <4>; reg-shift = <2>; clocks = <&ahb_clk>; - interrupts = ; - + /* NB: Polled mode - next line commented out + * interrupts = ; + */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 573309fe45823..d8b5d23abfab0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -39,6 +39,15 @@ &sdhci0 { microchip,clock-delay = <10>; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 18a535a043686..628a05d3f57ce 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -38,6 +38,15 @@ gpio-restart { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index d71f11a10b3d2..fb0bc3b241204 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -51,6 +51,15 @@ i2cmux_s32: i2cmux-3 { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl";