From patchwork Wed May 13 14:00:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546445 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF05990 for ; Wed, 13 May 2020 14:01:03 +0000 (UTC) Received: by mail.kernel.org (Postfix) id C78EE2065D; Wed, 13 May 2020 14:01:04 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72CC8207C3; Wed, 13 May 2020 14:01:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="e3jiO272" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 72CC8207C3 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378464; x=1620914464; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qbdBED/Z1XBg7VaaZopGpjjuifZRtcbEWF/Y+VJziDk=; b=e3jiO272xS+/xui+L7gYhXgxXyRL6HW9P8dZL1i+VjutI1JHzjEgsF3d oofoXX0pgv7M+K/VB5bNWDYgP9X2EqLAuK+tWXUEkfTtBAkvuFDzduhj1 bIikFLKfhVuXwHG0ToIi27071SUWKDfX8IwD2b7XqkOByNZ8E6uA+sR9D Avzy9xDW4r8eul24K5EB9wXpMbSUpaAQa8TiExvv07nSsZNAA5Nxn5+bH x+yoW8za0qxDb5C3ZV0vAlTnON53AS8wpCzzw60WH63aPqMFzjImz0FdZ IWbk8PhQJejqFsetHf4Q8khtDnGWjr5LHYEVTR/gtJh6ZnNEgTrHVAGKK Q==; IronPort-SDR: rBaFInmH5yPjnLhHZPsGcVpQf3K3KQUwci3AexoHvTqPZS4NkY7U3sK6ytEIGM7w75OuAT4Eqy ZSK1oGXC27mpC5lAw4/hIHehQtrDENUuytYqxhmjhWcX1vRlwnXc1K3YuylCJrBEa6YkV8ifF3 1mEm1G3X3EDAbC+Xn3Tk3u0smVYs2gxFQ2TwPpDwUjgzNgOP6b929wHjQC46PQ92BHNMBTJl+B AFoxVP/K+qGNjfQXqM+ukVULGETaj9Kc55CGQ9+ZkFNEk9bt6ggf9BXZQHrX2kZwNom+nLE31k dog= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="73314086" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:01:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:04 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:01:02 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Date: Wed, 13 May 2020 16:00:31 +0200 Message-ID: <20200513140031.25633-11-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This patch add spi-nand DT nodes to the applicable Sparx5 boards. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++++ .../boot/dts/microchip/sparx5_pcb134.dts | 22 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135.dts | 23 +++++++++++++++++++ 4 files changed, 72 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 330fd8b096d4c..60629861a5157 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -193,6 +193,26 @@ gpio: pinctrl@6110101e0 { interrupts = ; #interrupt-cells = <2>; + cs1_pins: cs1-pins { + pins = "GPIO_16"; + function = "si"; + }; + + cs2_pins: cs2-pins { + pins = "GPIO_17"; + function = "si"; + }; + + cs3_pins: cs3-pins { + pins = "GPIO_18"; + function = "si"; + }; + + si2_pins: si2-pins { + pins = "GPIO_39", "GPIO_40", "GPIO_41"; + function = "si2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index d8b5d23abfab0..94c4c3fd5a786 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -46,6 +46,13 @@ spi-flash@0 { spi-max-frequency = <8000000>; /* input clock */ reg = <0>; /* CS0 */ }; + spi-flash@1 { + compatible = "spi-nand"; + pinctrl-0 = <&cs1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <8000000>; + reg = <1>; /* CS1 */ + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts index feee4e99ff57c..9e8dc725a954a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -15,3 +15,25 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */ + spi-rx-delay-us = <500>; /* Tune for speed */ + /* Dedicated SPI2 interface */ + spi-flash@e { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + spi-max-frequency = <42000000>; + reg = <14>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts index 20e409a9be196..a31e10911dbaf 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */ + spi-rx-delay-us = <500>; /* Tune for speed */ + /* Dedicated SPI2 interface */ + spi-flash@e { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + spi-max-frequency = <42000000>; + reg = <14>; + }; +};