From patchwork Wed May 13 14:00:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B22E90 for ; Wed, 13 May 2020 14:00:44 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 65D6720693; Wed, 13 May 2020 14:00:45 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BBB920690; Wed, 13 May 2020 14:00:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="B83NU+8L" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3BBB920690 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378445; x=1620914445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E2LeTrXG5USlLqv6CmJsbBQmCdfRXDqsQ0KDLdpn/wA=; b=B83NU+8L4KbKDvFaQGXqcpKSEda4db5ppRK0bKpxPvsx4RQrgrGPN5xw /epOB2i+E4Roey71huKDOb8+6U9a/16yqNPo5bUAFeR0wjS4d0p+qkzR+ f8oqJDcCLGNzqsj/0f//71Bjl84Zm4Ed4hb2TWVYSEmMn8h6/TLh5c5w3 cn5+w40AzYUxAWVKwhYAI6TSi+gF4EfVkX84nA3ZnCSAz/aPFtAT+khnU 8l8taRxWVMi2gwFZojqUNVCs7jZeEksMIpI6HI0k9KwoJ8OMYx/zQKp0g jAyHeQQgwqEgF9S/92xBk1Ly4RIwyzT/oKkv63zwmysYnWIwOaBrLG7xW Q==; IronPort-SDR: fnwxvPcGQmcXFxqzx53KJMTcVAUAw6CucJ/tFsnpig2jxsTO5+7WvUQWlnhFHUS/c2LTWCinxk Ccy0u6/nP64oHUmfXqSWqSqMeCVJGnUEo1dEh0BbjPWAtZeAXcEivImlBrGMGRS/HnEqtji1Jp yPRZuRc3ai+OFB6qQ7jEW7rwfSKDZpSS2eP7pbq72WEPmGcU4YTAc/cfO3pRaYbNvpzVW5uX9N /zCcOHOQr0mcR2Y26nPKaysX8AVwbrTX04V0gKn4mWzdreHR4Qs9EI9W+0R7kOtzeOo4Bo2Zzd PXg= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="79447442" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:46 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:41 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Date: Wed, 13 May 2020 16:00:22 +0200 Message-ID: <20200513140031.25633-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 With this change a SPI controller can be added without having a IRQ associated, and causing all transfers to be polled. For SPI controllers without DMA, this can significantly improve performance by less interrupt handling overhead. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/spi/spi-dw.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) -- 2.26.2 diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 31e3f866d11a7..e572eb34a3c1a 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -19,6 +19,8 @@ #include #endif +#define VALID_IRQ(i) (i >= 0) + /* Slave spi_dev related */ struct chip_data { u8 tmode; /* TR/TO/RO/EEPROM */ @@ -359,7 +361,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_enable_chip(dws, 1); return ret; } - } else if (!chip->poll_mode) { + } else if (!chip->poll_mode && VALID_IRQ(dws->irq)) { txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); dw_writel(dws, DW_SPI_TXFLTR, txlevel); @@ -379,7 +381,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, return ret; } - if (chip->poll_mode) + if (chip->poll_mode || !VALID_IRQ(dws->irq)) return poll_transfer(dws); return 1; @@ -487,11 +489,13 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) spi_controller_set_devdata(master, dws); - ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), - master); - if (ret < 0) { - dev_err(dev, "can not get IRQ\n"); - goto err_free_master; + if (VALID_IRQ(dws->irq)) { + ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, + dev_name(dev), master); + if (ret < 0) { + dev_err(dev, "can not get IRQ\n"); + goto err_free_master; + } } master->use_gpio_descriptors = true; @@ -539,7 +543,8 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) if (dws->dma_ops && dws->dma_ops->dma_exit) dws->dma_ops->dma_exit(dws); spi_enable_chip(dws, 0); - free_irq(dws->irq, master); + if (VALID_IRQ(dws->irq)) + free_irq(dws->irq, master); err_free_master: spi_controller_put(master); return ret;