From patchwork Wed May 13 14:00:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8BC390 for ; Wed, 13 May 2020 14:00:55 +0000 (UTC) Received: by mail.kernel.org (Postfix) id E32C120690; Wed, 13 May 2020 14:00:56 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B2D52065D; Wed, 13 May 2020 14:00:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1i6RQ+TK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B2D52065D Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378457; x=1620914457; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FaO/GETf8z+ABiKcnmBIXRkSMrzTv7Y0Bt8RBuG3pBE=; b=1i6RQ+TKaI71/CH22THmpfAWlWwIw0sG9Z9+D8KQewdSvrsfLPjDVo6A pM2Ucq/uq5NjvC3XK07FzPfqGNJ95PHzFH5/VsyZIT9d7FYTXUcqFKTsN EYydxQXXugDvwOjziAnrU1Ar4dm6Uf9B++PBSYesGIVsM+bXJOBdqInXW YUIRtp0TzuVnpCD8MlercT7GBL6RZrzEMNBdeMIVA5IxBJhdOBWBLR9x0 MIvtIvWY8zCxfTtfcRxOi9Kpk43Dfe7Ppr51lqIGpKPc6rYJSX3wStqqg 0umVAG4zGM0bviyraaVv1yrOeZtcO56YnfVoEJ8ZvehOWayiyogZ8MVO4 A==; IronPort-SDR: sw7/+Xl09HJPBB3WW6IIefnitHCp5+tjOGx6sM6RkNeZoJSIntXCAfjjBR62S4wTzy6ugH94Gg bfgIDneKlZZhULpZV3vmc4uAzmk310dee5pWvaJ0wmNA6tEYz9Cy2jfKp3DPu4R22gArmCam4S JxdSCru1oe/jNhAqTXe/yaRS63Q1182oBqfQ6iZ8/kMFOb/rz2mfUPrpDW5Hr8BH+Nr4rpmqjZ egSu78qhKxdJ8RcWuLdUKFe52moXN0aTf6iho2dHUa0H8Bodhir/lju4/83rwVwDsM5r/LVatJ PCA= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="79447556" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:57 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:52 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team , Rob Herring CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Date: Wed, 13 May 2020 16:00:27 +0200 Message-ID: <20200513140031.25633-7-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add DT bindings for the Sparx5 SPI driver. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- 1 file changed, 39 insertions(+), 10 deletions(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml index a3ac0fa576553..8beecde4b0880 100644 --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml @@ -23,15 +23,23 @@ properties: enum: - mscc,ocelot-spi - mscc,jaguar2-spi + - microchip,sparx5-spi interrupts: maxItems: 1 reg: minItems: 2 - items: - - description: Designware SPI registers - - description: CS override registers + maxItems: 3 + oneOf: + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - description: Direct mapped SPI read area. If provided, the + driver will register spi_mem_op's to take advantage of it. clocks: maxItems: 1 @@ -43,6 +51,23 @@ properties: enum: [ 2, 4 ] maxItems: 1 + spi-rx-delay-us: + description: | + The delay (in usec) of the RX signal sample position. This can + be used to tne the RX timing in order to acheive higher + speeds. This is used for all devices on the bus. + default: 0 + maxItems: 1 + + interface-mapping-mask: + description: | + On the Sparx5 variant, two different busses are connected to the + controller. This property is a mask per chip-select, indicating + whether the CS should go to one or the other interface. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maxItems: 1 + required: - compatible - reg @@ -50,11 +75,15 @@ required: examples: - | - spi0: spi@101000 { - compatible = "mscc,ocelot-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x101000 0x100>, <0x3c 0x18>; - interrupts = <9>; - clocks = <&ahb_clk>; + #include + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; };