From patchwork Fri Jun 19 11:31:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11613951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FEB014E3 for ; Fri, 19 Jun 2020 11:31:42 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 1C57A21527; Fri, 19 Jun 2020 11:31:42 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6B1A207FC; Fri, 19 Jun 2020 11:31:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="vXNIaIq9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6B1A207FC Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592566301; x=1624102301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kjTc0lDvbX2q6sDCdQDYyLFYSA/iqLUPgJ9XmdVLoX8=; b=vXNIaIq9J2XS5NkUGxLLQXE0WjdxSXYVi/VWSLsY55T1FXN1/lfxtTLg swHf20UKSOFFStxTznO3jUrjiU6Zb0U4TYHurxd1vq6qw8UscDWJcvifb I7y2hvWSRzCKpynfDffS3bpl4zZkwdfOoSM7ZwcJ/WGuY5PyLCEdZ7zoC NS+e6dba8y4m4lYWUr+D18CoHXU+/fwQ/Qq/YjmiGgPeexPA2jkTpBswA ekvpLfSCx+c/quMdfTbIk7m3ed7Rq726BL4lUhVNQZeSdVqlSWyfHoQXh L0EKYzcQkS2xA51t3mA5+1AuPv0GMY6BmT7cCVQwyVVaksr6Mvm3X9s80 g==; IronPort-SDR: 5tCxH3ZJH1R1MOehWYbR4JGvWH+LB4qV1roaxoIyERCaBUOysCw7AgLP7tYaRj14i25qWM+vrV u2kq8M87IAhUemDJBkbUetsqUXoYpITgnjXHPd2NsWGC8UFo6mXVOi3P13s+yX4cTB4TwkPyYl ORM4KQcnCevmqr0r1/qIToyhzUabojpcvQID7dzgMSZ8QCtiG5K19zeMxHarNB29P65aMf/l71 YvJCZGmp5nikwJRhgdvarphCqsAepOmPQhO09ceA3xtUqdKa0Io+xqK7JGhcpDRLDG8bD2/4d1 2KI= X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="84298531" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Jun 2020 04:31:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 19 Jun 2020 04:31:30 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 04:31:28 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v2 2/6] arm64: dts: sparx5: Add SPI controller Date: Fri, 19 Jun 2020 13:31:17 +0200 Message-ID: <20200619113121.9984-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619113121.9984-1-lars.povlsen@microchip.com> References: <20200619113121.9984-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds a SPI controller to the Microchip Sparx5 SoC Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 7e811e24f0e99..2404bcc08b89d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -14,6 +14,7 @@ / { #size-cells = <1>; aliases { + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; }; @@ -155,6 +156,19 @@ uart1: serial@600102000 { status = "disabled"; }; + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x6 0x00104000 0x40>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + timer1: timer@600105000 { compatible = "snps,dw-apb-timer"; reg = <0x6 0x00105000 0x1000>;