From patchwork Tue Jul 14 16:13:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 292C860D for ; Tue, 14 Jul 2020 16:13:46 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 224842253D; Tue, 14 Jul 2020 16:13:46 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 00BE52075B; Tue, 14 Jul 2020 16:13:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00BE52075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: 7OQc+w7H++K1yyXl4aEHmvQIql7bxJDpSbDzxHLppU4sVDamvOzglt9hocLdqDNNvI4fw8sz2g QxsrivmrGXTQ== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738122" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738122" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:45 -0700 IronPort-SDR: JS6+rD7t2ni19gzPe59pM5E/WFoyOHixccFbuMzfUrOjK1XB3x5KZ9QaXbRJnlor8kqVVXd1c6 GmiABp1ZwHEQ== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930553" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:42 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 3/7] dt-bindings: clock: Add Keem Bay clock IDs Date: Tue, 14 Jul 2020 17:13:01 +0100 Message-Id: <20200714161305.836348-4-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add clock dt-bindings for Keem Bay SoC. Signed-off-by: Daniele Alessandrelli --- include/dt-bindings/clock/keembay-clocks.h | 188 +++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 include/dt-bindings/clock/keembay-clocks.h diff --git a/include/dt-bindings/clock/keembay-clocks.h b/include/dt-bindings/clock/keembay-clocks.h new file mode 100644 index 000000000000..4ad6616ee8e0 --- /dev/null +++ b/include/dt-bindings/clock/keembay-clocks.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2020 Intel Corporation. + * + * Device tree defines for clocks in Keem Bay. + */ + +#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H +#define __DT_BINDINGS_KEEMBAY_CLOCKS_H + +/* CPR_PLL region. CLK_ID: 0 - 11 */ +#define KEEM_BAY_A53_PLL_START_ID (0) +#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0) +#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1) +#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2) +#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3) +#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4) +#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5) +#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6) +#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7) +#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8) +#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9) +#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10) +#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11) +#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3) + +/* A53_CPR region. CLK_ID: 12 - 30 */ +#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1) +#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0) +#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1) +#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2) +#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3) +#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4) +#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5) +#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6) +#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7) +#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8) +#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9) +#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10) +#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11) +#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12) +#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13) +#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14) +#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15) +#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16) +#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17) +#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18) +#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3) + +/* A53_CPR_AUX region. CLK_ID: 31 - 57 */ +#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1) +#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0) +#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1) +#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2) +#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3) +#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4) +#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5) +#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6) +#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7) +#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID + 8) +#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9) +#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10) +#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11) +#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID + 12) +#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13) +#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14) +#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 15) +#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID + 16) +#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID + 17) +#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18) +#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19) +#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID + 20) +#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21) +#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID + 22) +#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23) +#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24) +#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25) +#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 26) +#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF) + +/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */ +#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1) +#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0) +#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1) +#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2) +#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3) +#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4) +#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5) +#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6) +#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7) +#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8) +#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9) +#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10) +#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11) +#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12) +#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13) +#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14) +#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15) +#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16) +#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17) +#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18) +#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19) +#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20) +#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21) +#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22) +#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23) +#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24) +#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE) + +/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */ +#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1) +#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0) +#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1) +#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2) +#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3) +#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4) +#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5) +#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6) +#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7) +#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8) +#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9) +#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10) +#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11) +#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12) +#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13) +#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14) +#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX) + +/* DSS_CPR region. CLK_ID: 98 - 109 */ +#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1) +#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0) +#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1) +#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2) +#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3) +#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4) +#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5) +#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6) +#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7) +#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8) +#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9) +#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10) +#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11) +#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500) + +/* USS_CPR region. CLK_ID: 110 - 116 */ +#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1) +#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0) +#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1) +#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2) +#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3) +#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4) +#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5) +#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6) +#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST) + +/* MSS_CPR region. CLK_ID: 117 - 129 */ +#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1) +#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0) +#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1) +#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2) +#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3) +#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4) +#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5) +#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6) +#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7) +#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8) +#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9) +#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10) +#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11) +#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12) +#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM) + +/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */ +#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1) +#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0) +#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1) +#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2) +#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3) +#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4) +#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5) +#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6) +#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7) +#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8) +#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC) + +#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1) + +#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */