From patchwork Tue Jul 14 16:13:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11663169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB72860D for ; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) Received: by mail.kernel.org (Postfix) id A5D9E2251E; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 844982075B; Tue, 14 Jul 2020 16:13:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 844982075B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: t3ZFXr+cWOJ55BiTQvjrPDgB2isca0D9pkq18HYv1yE5jZQpEQAqfJNCST5+pTWfUM7O+/IbTn zUTIs5yyNmCQ== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="213738135" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="213738135" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:49 -0700 IronPort-SDR: w02oRpL+zy/c4+nw16rV03VnHTGrSz40xWcmPlrviQAykU91o0+Mtr+DbOtNcYjXFn8CwLJexJ Ii7zVmI/uHug== X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="485930577" Received: from yagellee-mobl.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.20.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 09:13:45 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v3 4/7] dt-bindings: power: Add Keem Bay power domains Date: Tue, 14 Jul 2020 17:13:02 +0100 Message-Id: <20200714161305.836348-5-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> References: <20200714161305.836348-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add power domain dt-bindings for Keem Bay SoC. Signed-off-by: Daniele Alessandrelli --- include/dt-bindings/power/keembay-power.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/power/keembay-power.h diff --git a/include/dt-bindings/power/keembay-power.h b/include/dt-bindings/power/keembay-power.h new file mode 100644 index 000000000000..1385c42f897d --- /dev/null +++ b/include/dt-bindings/power/keembay-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2020 Intel Corporation. + * + * Device tree defines for power domains in Keem Bay. + */ + +#ifndef __DT_BINDINGS_KEEMBAY_POWER_H +#define __DT_BINDINGS_KEEMBAY_POWER_H + +#define KEEM_BAY_PSS_POWER_DOMAIN 0 +#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1 +#define KEEM_BAY_VDEC_POWER_DOMAIN 2 +#define KEEM_BAY_VENC_POWER_DOMAIN 3 +#define KEEM_BAY_PCIE_POWER_DOMAIN 4 +#define KEEM_BAY_USS_POWER_DOMAIN 5 +#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6 + +#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */