| Message ID | 20200726043948.1357573-2-daniel@0x0f.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ARM:mstar: DT filling out | expand |
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b99bb435bb5..6bc55fdbee04 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -45,7 +45,8 @@ soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0x16001000 0x16001000 0x00007000>, - <0x1f000000 0x1f000000 0x00400000>; + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; gic: interrupt-controller@16001000 { compatible = "arm,cortex-a7-gic"; @@ -78,6 +79,11 @@ pm_uart: uart@221000 { clock-frequency = <172000000>; status = "disabled"; }; + }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; }; }; };
All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- arch/arm/boot/dts/mstar-v7.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)