From patchwork Sun Jul 26 04:39:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11685479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74379912 for ; Sun, 26 Jul 2020 04:40:01 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6DE0420773; Sun, 26 Jul 2020 04:40:01 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pj1-f66.google.com (mail-pj1-f66.google.com [209.85.216.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B71B2053B for ; Sun, 26 Jul 2020 04:40:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="JKPAyqM7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4B71B2053B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pj1-f66.google.com with SMTP id k1so7356420pjt.5 for ; Sat, 25 Jul 2020 21:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TOWjKhpTAUxQGzRJ9viFhazH/fxYC7lH/fcb5nYvYF8=; b=JKPAyqM7DYs8ZxV2wxCYxmRX9YIbRDi8htfCF4Iosv2ft0c+yX6CcF7e8oGlxBFZQd tbEMr76Ja2sFM5x3o77uGnz75XZRJiOwUdwOEadXmo5WE99JA8Ajkj3WLDXOPCHiR3oz KZ6YYQZ2O6yNgOvDuse6P9nGN9NGm6FfAmDrI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TOWjKhpTAUxQGzRJ9viFhazH/fxYC7lH/fcb5nYvYF8=; b=a1L4RI7iBe9MDBchNDq7k56XXQcgYddm4O6DaNAWNVM/kL4KMUYd6LJC7hQdIPN0+W qbYPwwPA8+YLj2VSEZfWNlUcyzGWoOo2wYnPztGtUvT7RAjj9UBHumuawMAL/e5F1Hs/ cZi5oSHeKsHEuXDZXL3FoubdkWCKs15hINNlDQez8PprCfVVulBYm2Bxq5AYvQSStAh7 HMs7FFjUV9Is7HAR38Kl1rVI9Q/1stklrCaLHdBOuIunrefT4aRkkJw90yEjbQBZ9nrR OesP0sw7zW93H14uctoH3b1LB7A/ez0cdu68AiB7xRgoTFIuJekr2oY6NHlPkuc3j0BV bjgQ== X-Gm-Message-State: AOAM531NOXf6F+PHw3YGOMYtmvEc46A/tg0SueEAf3inu/lUNWGo1PIx xAaT0JylDnnHj3iOK5iRL+4O4Bg11DU= X-Google-Smtp-Source: ABdhPJxh4sRsd07sZyUTJSxYKMWazSwAyP3irmtzA7+FVUKFIaegODvr1sdEwiFJSqJADyhWgO0+AA== X-Received: by 2002:a17:90b:11c7:: with SMTP id gv7mr12685172pjb.175.1595738398347; Sat, 25 Jul 2020 21:39:58 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id t1sm10507372pje.55.2020.07.25.21.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Jul 2020 21:39:57 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH 1/7] ARM:mstar: Add IMI SRAM region Date: Sun, 26 Jul 2020 13:39:42 +0900 Message-Id: <20200726043948.1357573-2-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200726043948.1357573-1-daniel@0x0f.com> References: <20200726043948.1357573-1-daniel@0x0f.com> MIME-Version: 1.0 All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b99bb435bb5..6bc55fdbee04 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -45,7 +45,8 @@ soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0x16001000 0x16001000 0x00007000>, - <0x1f000000 0x1f000000 0x00400000>; + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; gic: interrupt-controller@16001000 { compatible = "arm,cortex-a7-gic"; @@ -78,6 +79,11 @@ pm_uart: uart@221000 { clock-frequency = <172000000>; status = "disabled"; }; + }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; }; }; };