From patchwork Mon Jul 27 08:42:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11686563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 18C5913B1 for ; Mon, 27 Jul 2020 08:42:32 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 138B62074F; Mon, 27 Jul 2020 08:42:32 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DCB6C206E7; Mon, 27 Jul 2020 08:42:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="zJmf4w1m" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DCB6C206E7 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1595839351; x=1627375351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5wjLdEVL0+5wkcGZWXGlwE+jpjsqmabT9Jw33q+g7no=; b=zJmf4w1mXUuYhzRFsyDwqzAhtLj8tIAmnf5tX/v/2YkflrUHncp2Mxgi 5MivU++Z3EGH3OMozrTPPJ7qJn7RrK7RoEHij5CWSpfOptDtyKvcDepep Ww6AUqJ8GSScNas231yVCE+UX1rzX8D7qoGAfOdMMwypcXkglo+vFIVtO lfjMLcFznVdu3FgGiEWKq456d5aYRwobMR71Y5H3t0j/x8yZ+2mEp8RWB CH3SlZfUBXuGVzL12sNFEUnluLfXQ8TMha4fv3Vy72R3cN0P5zF5LTCXs 5F6ZFkL6Bp+TtQm4q2H7zHJ2NmYvsEu4oZQxCt4Uu/CYVsz9Qc+ZRy3XE Q==; IronPort-SDR: Q7Tk98p1VpkhnBLBFv5chqOFQVGahl7JqC095p8CeUs+hARbSOozs5d8/PkfksO2D5Yxaq4Ky0 U8/tXXH9e1pGwvxb+u8dB7r2nJVtiaZo6N8lqGL3El18dZeyGe5orsc6FN4XLMQFeC221r6Qjy 2ZkmkNkRuujoBmoDiavwx3P/6Gl/Dj21HcXUJNZqurgFKbITFfePrNI+iBwh2MrekxpO8xBCl9 /ZAiCWkzoPTtKVrI+HHG6SH5UnjR9k8g/O07aI1R6j1D+66U1kpNWnbgG6qclZYyzNEx3T/TSd Z0c= X-IronPort-AV: E=Sophos;i="5.75,402,1589266800"; d="scan'208";a="85470325" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Jul 2020 01:42:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 27 Jul 2020 01:42:29 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 27 Jul 2020 01:42:26 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH v4 02/10] arm64: sparx5: Add support for Microchip 2xA53 SoC Date: Mon, 27 Jul 2020 10:42:03 +0200 Message-ID: <20200727084211.6632-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200727084211.6632-1-lars.povlsen@microchip.com> References: <20200727084211.6632-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Signed-off-by: Lars Povlsen --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 68f21d46614c4..13553b77ed4f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2111,6 +2111,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +N: sparx5 + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8dd05b2a925c5..8939e4e6e34c2 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM