From patchwork Mon Jul 27 08:42:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11686569 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E451C722 for ; Mon, 27 Jul 2020 08:42:37 +0000 (UTC) Received: by mail.kernel.org (Postfix) id DFF872074F; Mon, 27 Jul 2020 08:42:37 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B447E206E7; Mon, 27 Jul 2020 08:42:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kZQOAfu0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B447E206E7 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1595839357; x=1627375357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3uw3KYGVcOCYb2y09i3eYMZ3PWc3Td6IdI8eVYh5wfE=; b=kZQOAfu0yWk/wdDmaRb2oR0XswukFEavJagAtFJa/dryO+hTrfrDG4s5 SzNRXxj4RNgRJkFHQGht9nOaQ/Kk1GE7075EHaSfnj+1T9kabeTD0Bc9M 7so5RgIs+85x4FZSv2+wRn+jpoRZynz5GuCx+QVkuISbnhOF5RmyFivGG wMsNSrWkHnLlvA3Y/wh+uFmhcBQi4DAMrsc55Y3NEbVq89HEkuI1lCcH9 gar27yQGdGveAuBhm1p/mw8GPPoTdPOjk+7hDZiHbhNVOUuri1H0mGz5o 3aCvRueNBqWcgsCVA/Koh6iY3Tqof2F9uChOMcNYA/fFOWJgAYTnLm4uG Q==; IronPort-SDR: YZh9mJqVARAm9H6/Vx1FUO050ldgt3+ieHM+AhdtJRfU7www9B30+QAYnZDHgWAUdCEbqInXB7 BxuaSJOGkdN410D0qVLHH8phzNYpifaJeDhR7jCBXMwkUO0UER73vSefjV1/v2WbSEj2GOJ+64 IuZjFWKQMzTxaKGbKCFRLDLeF0Ka34pkF5jaO8nYGs8NeRDS2I15h9uxV9BtvX8oe9woDBlG9j MyGzZ3pNiCdDPRhMzaISFC7V7uFU7n91rZIS5olTTd/S+5ywaSMQ59YaTWs6bvKZw8KRlV5GDl Bew= X-IronPort-AV: E=Sophos;i="5.75,402,1589266800"; d="scan'208";a="85470384" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Jul 2020 01:42:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 27 Jul 2020 01:42:35 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 27 Jul 2020 01:42:33 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH v4 04/10] arm64: dts: sparx5: Add pinctrl support Date: Mon, 27 Jul 2020 10:42:05 +0200 Message-ID: <20200727084211.6632-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200727084211.6632-1-lars.povlsen@microchip.com> References: <20200727084211.6632-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add pinctrl support to the Microchip Sparx5 SoC. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 +++++++++++++++++++ .../dts/microchip/sparx5_pcb134_board.dtsi | 5 ++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 5 ++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 4a54b7d039167..baf4176ce1dfe 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -109,6 +109,8 @@ gic: interrupt-controller@600300000 { }; uart0: serial@600100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; @@ -120,6 +122,8 @@ uart0: serial@600100000 { }; uart1: serial@600102000 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; @@ -138,5 +142,27 @@ timer1: timer@600105000 { interrupts = ; }; + gpio: pinctrl@6110101e0 { + compatible = "microchip,sparx5-pinctrl"; + reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart2"; + }; + + }; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 005cf6babb9b3..9b2aec400101b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 005cf6babb9b3..9b2aec400101b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; };