From patchwork Mon Jul 27 08:42:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11686579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8096513B1 for ; Mon, 27 Jul 2020 08:42:47 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 7A16A20759; Mon, 27 Jul 2020 08:42:47 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F93E20719; Mon, 27 Jul 2020 08:42:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="fAeM8Q6x" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F93E20719 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1595839367; x=1627375367; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5MLPYjoTsh+TV8uVlGQyI3alO8753yChgHddi7BhCF8=; b=fAeM8Q6xl8SES3TRL4vyHLyyTHxj6SeYA2+VvCs59NW5OXVUNYj2mCNF /x1qEmIa75xepbEKiJqUpZKv9ZWjM2pDALMvOf7gdVI+9gIkkg6ziwgTl HR+rZrMltLwj1uDSz8s74p9tn2664z471A/hxCWQFS8yIqI4x+s7srrDi SGHm9NcZweAlNiuI0+ynf816k6Uzigg1Xt+t4yNDyYhmmwSgVwO42U2M7 rocvX+6/FTbLs5gKSaEuHLltO17yky8d85QdxhkkM6IqOJRe/58DOa/pS ++8Xdl7RVeZfcRdYoweoLEbjy/YbZICDM1B5qS1AOt5iHT9yssvcz6wK1 w==; IronPort-SDR: gw4bQ4piImdVZxzMe0uD+Vv822Zj4ziUfjOp1qw6OWY3QTeN/BC2CtsunB0XtcpKbFiODd4L67 epzktl0eKfRqz3LWalqn69fIRUpphexjT3X2LiK3HfNKYHiESaAl82I0P4lMhsW2q1BcBL65o0 4aHjcsirqcwAbdI1Al3RJe/WB1hM66Bls4gMkKr2OyKiHpqqnyhPS2l7vBMmcp6PPrxkDUOSFW y49jlKL7mPrfnIP7x6zg5pnIxqOr5HaAqBlwH95p9UWOwg0uRmnwkjA3yHAeMEGZhsRZHwKVU+ iJ0= X-IronPort-AV: E=Sophos;i="5.75,402,1589266800"; d="scan'208";a="85470448" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Jul 2020 01:42:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 27 Jul 2020 01:42:00 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 27 Jul 2020 01:42:42 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni , Rob Herring Subject: [PATCH v4 07/10] dt-bindings: clock: sparx5: Add bindings include file Date: Mon, 27 Jul 2020 10:42:08 +0200 Message-ID: <20200727084211.6632-8-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200727084211.6632-1-lars.povlsen@microchip.com> References: <20200727084211.6632-1-lars.povlsen@microchip.com> MIME-Version: 1.0 The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Signed-off-by: Lars Povlsen Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- include/dt-bindings/clock/microchip,sparx5.h | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,sparx5.h diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h new file mode 100644 index 0000000000000..4b04dabacec2c --- /dev/null +++ b/include/dt-bindings/clock/microchip,sparx5.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 Microchip Inc. + * + * Author: Lars Povlsen + */ + +#ifndef _DT_BINDINGS_CLK_SPARX5_H +#define _DT_BINDINGS_CLK_SPARX5_H + +#define CLK_ID_CORE 0 +#define CLK_ID_DDR 1 +#define CLK_ID_CPU2 2 +#define CLK_ID_ARM2 3 +#define CLK_ID_AUX1 4 +#define CLK_ID_AUX2 5 +#define CLK_ID_AUX3 6 +#define CLK_ID_AUX4 7 +#define CLK_ID_SYNCE 8 + +#define N_CLOCKS 9 + +#endif