From patchwork Tue Jul 28 10:03:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11688797 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 006706C1 for ; Tue, 28 Jul 2020 10:03:41 +0000 (UTC) Received: by mail.kernel.org (Postfix) id EF16322C9E; Tue, 28 Jul 2020 10:03:40 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5C57207E8 for ; Tue, 28 Jul 2020 10:03:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="SKCdPVmL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5C57207E8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pl1-f196.google.com with SMTP id p1so9626619pls.4 for ; Tue, 28 Jul 2020 03:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MLsnjIcx6O7hBUqO+ly4gJ/BT4WlJTFqju/5sXIimIg=; b=SKCdPVmLWJF2bLrtZU3g+eZO6Jvjk2z4+jmQXQol4BWOQK4BYolKrUCLan1cceEyYJ XlJqjlKhsQsOGcSuJzmzVXGgYVOY7CIXKyo+2t8BH0Pw8yXqgL4huJaNbNEl34vjn/Zs 3o67Tt6q5uqH889AcUvizaQWxtfULuH9wC+SA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MLsnjIcx6O7hBUqO+ly4gJ/BT4WlJTFqju/5sXIimIg=; b=czwzIM64oKtQmpmxk3L8VXKsWxmiIW9QFuoVONbaVM1cBAgffnshWuPXCxcYAL1o2D wCnCGchtbs0W1RA7BJ9WmsRTu5X+t6FxzYip8OR2XOYxcbwEhSJh9s3TLUec1oh/GW+r /cYXsXS56jsH54VWUcSJe1lY3PKkuUdnoB+3QY69FnL9CbQyLC9ePMoRMZtNc5hNXP+8 Yc3kvAqHhr8TwBOICvWhTgiEeg2c7M7QtAJY6cQngveKqkkXnHcqclTLFY1SpqNnJyUa FWMBwc2WhlmNqV5z7vKtiYI14s/YOiMbUsGb7BZwBTTiarUgTHUFivUkPSki1sGQWw5D +7YA== X-Gm-Message-State: AOAM531vxbA+xE62a+fxzYBR9VYeKHG+oKzo6v/F+ZXJrfjO+YEfIWRc /6O8tLuzyA+Nga+WoGxt5huoMTf6RtE= X-Google-Smtp-Source: ABdhPJxSjatle00lO8xbMWFh3tR143iGH9zfFmSLzFijKNfxg6ikjSpg1obUHnDL0D8z4jadb44Zfg== X-Received: by 2002:a17:90a:ce0c:: with SMTP id f12mr3828042pju.19.1595930619871; Tue, 28 Jul 2020 03:03:39 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id u66sm17779018pfb.191.2020.07.28.03.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 03:03:39 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arnd@arndb.de, robh@kernel.org, Daniel Palmer Subject: [PATCH v2 3/9] ARM: mstar: Add IMI SRAM region Date: Tue, 28 Jul 2020 19:03:15 +0900 Message-Id: <20200728100321.1691745-4-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728100321.1691745-1-daniel@0x0f.com> References: <20200728100321.1691745-1-daniel@0x0f.com> MIME-Version: 1.0 All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b99bb435bb5..1941f88a69a5 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -45,7 +45,8 @@ soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0x16001000 0x16001000 0x00007000>, - <0x1f000000 0x1f000000 0x00400000>; + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; gic: interrupt-controller@16001000 { compatible = "arm,cortex-a7-gic"; @@ -79,5 +80,10 @@ pm_uart: uart@221000 { status = "disabled"; }; }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; + }; }; };