From patchwork Thu Jul 30 13:00:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11693013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55164138A for ; Thu, 30 Jul 2020 13:02:41 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 4E6F5208A9; Thu, 30 Jul 2020 13:02:41 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AE2720842 for ; Thu, 30 Jul 2020 13:02:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="gwMEPelP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AE2720842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pl1-f193.google.com with SMTP id t10so8716376plz.10 for ; Thu, 30 Jul 2020 06:02:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1mAnNNAZfPfzyF88X1fOSRFSMBROfjHobKP31kxfdOc=; b=gwMEPelPCgps8yK/7P5U/nJeMrOiHbmuTpDjW3s5ScDbElTNZlQ48BdHcUjSr3otHT f9gqkU53F4K8jQ1FDa9L9zSnEylVfJq7FvPbjC1rGH6N21g8UqQWPJfl6hHzzKksHuBo K41e4E6uwPaneffN2lXMuphGRuQzOqFIEcuR4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1mAnNNAZfPfzyF88X1fOSRFSMBROfjHobKP31kxfdOc=; b=W/1ApdEKD7Hqtg6oQ+/npb6qjdnMfKmO7WPKBywEQuSu9kucblNest1zAZAkrWyabM mJmNp/IIwdejKGEWjRQ4cdG5n4JOV59ST9mXfwEYZ68Rbjc7V09tS2dF9sh6QHASdSMR w0KTNTc+cyCqqYvpLI50TCcjgz5MjiDWlZvuofoKN9wE7q29myohUVQppw9fwWFfVr28 dp7TB/LZHvqyjVfSSr4z00Oes6su2jJeIhGK8y3UFr9RFCjlurByYEK0LooR35ZJJnmP Mn6hWgKJ+oix+Q7AVPY/cICAyM4/tho6vRlXOktw9Dh8ZPWxAD4dV8469eDojt+bYpyA YpOg== X-Gm-Message-State: AOAM531Yhwr+4cvYFQE4T5OamW4lTFkldL27XDIWg4msuYxptgjdiY5t do/XpmIukcOx6jfkbmRob8sxj/lvz+o= X-Google-Smtp-Source: ABdhPJxNukSgN9Qo/irUQx6o1//oMXDCOpTPEIiCWNID4Fq0bqW7VIUaf+7hbETLGyIkE09W+8cNcQ== X-Received: by 2002:a62:8307:: with SMTP id h7mr3159636pfe.149.1596114159579; Thu, 30 Jul 2020 06:02:39 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id b13sm6758704pgd.36.2020.07.30.06.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2020 06:02:38 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux@armlinux.org.uk, w@1wt.eu, Daniel Palmer Subject: [RFC PATCH 3/3] ARM: mstar: Add interrupt controller to base dtsi Date: Thu, 30 Jul 2020 22:00:44 +0900 Message-Id: <20200730130044.2037509-4-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200730130044.2037509-1-daniel@0x0f.com> References: <20200730130044.2037509-1-daniel@0x0f.com> MIME-Version: 1.0 Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7 dtsi. All of the know SoCs have both and at the same place with their common IPs using the same interrupt lines. Signed-off-by: Daniel Palmer Tested-by: Willy Tarreau --- arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..2b3bb0886d1a 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,26 @@ reboot { mask = <0x79>; }; + intc_fiq: intc@201310 { + compatible = "mstar,msc313-intc-fiq"; + interrupt-controller; + reg = <0x201310 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <96>; + mstar,nr-interrupts = <32>; + }; + + intc_irq: intc@201350 { + compatible = "mstar,msc313-intc-irq"; + interrupt-controller; + reg = <0x201350 0x40>; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + mstar,gic-offset = <32>; + mstar,nr-interrupts = <64>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>;