From patchwork Fri Oct 2 13:34:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11813555 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53A52139F for ; Fri, 2 Oct 2020 13:34:38 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 4E3EA21D94; Fri, 2 Oct 2020 13:34:38 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pj1-f65.google.com (mail-pj1-f65.google.com [209.85.216.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D38D022207 for ; Fri, 2 Oct 2020 13:34:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="oCMWc6Jj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D38D022207 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pj1-f65.google.com with SMTP id t7so827245pjd.3 for ; Fri, 02 Oct 2020 06:34:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6W9k3ndaa9cRCwcQ1M/asEuo1OK8FOTIyDJ+tvTfSmU=; b=oCMWc6Jj4ktZjU2Abv3j8Jo7vqF5s3w07Ee2so2ulyh/HCR9TQnPRmZsGt75tpet1z znJdIuBUpgrqVS4Obqt7rsJhrsQhorjU6izHw4x3tQI1D79kvecwXfPOtQSf9Yv/6WPt yz+zJu/NROjZFu+JUO9rJ145yw15SArOMUKek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6W9k3ndaa9cRCwcQ1M/asEuo1OK8FOTIyDJ+tvTfSmU=; b=ry7SEVRo6EPbCdlXoUipCDr2Zy4AL2ISNMMnjzcKTTliS6dpQynSeJmcjLLoK7UCZR SzYzWSjxAHQyIAzDQUzEx3s+5dXyHK+H8CRoDtvnc3K0/wvrK4//YFI5s4qqRKs+93mQ SMHTAV70UOhN+GyIBpIUVjnypnhwRg9WMidoSkZOyLtegnBmXf/YKVNGZzXMutI0GFq3 GgLO7xNY3l9/wVwmtCn0viLo7yIl4AceJRmYIJu+Eop6PxccfI5/W8Yh8OcRbdMRj5PB 7MLAsdONjpuIpBoMwyM8oabiHlSqiVRvuHqRfZAvF+9n1lzjJOKgEqQARE/6ahuSU+ov 0Ilw== X-Gm-Message-State: AOAM530VLoE5aC+uVgzsY0mjTeEez9ltOujac1XB0Tv5Zm/zxoxYNzGE Ho869vBQ/24Wad5zG/HG2xCX9/8RkKsRPA== X-Google-Smtp-Source: ABdhPJwSI1/I/1oq6fVw/wrmjpIzo5Uq4okkncEKBWITlbuxGxkjLW+1YPYtbxPqs3I2cpdnlbwklw== X-Received: by 2002:a17:90a:8d05:: with SMTP id c5mr2757642pjo.222.1601645676968; Fri, 02 Oct 2020 06:34:36 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id k14sm1708219pjd.45.2020.10.02.06.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2020 06:34:36 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, mark-pk.tsai@mediatek.com, arnd@arndb.de, maz@kernel.org, Daniel Palmer Subject: [PATCH v2 1/5] ARM: mstar: Select MStar intc Date: Fri, 2 Oct 2020 22:34:14 +0900 Message-Id: <20201002133418.2250277-2-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201002133418.2250277-1-daniel@0x0f.com> References: <20201002133418.2250277-1-daniel@0x0f.com> MIME-Version: 1.0 MediaTek recently introduced support for the MStar interrupt controller that is also present in some of their chips as well as the MStar/Sigmastar chips. Almost all of the peripheral interrupts go through an instance of this controller in MStar/SigmaStar Arm v7 chips so we want to select it if CONFIG_ARCH_MSTARV7 is selected. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 52744fe32368..576d1ab293c8 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -3,6 +3,7 @@ menuconfig ARCH_MSTARV7 depends on ARCH_MULTI_V7 select ARM_GIC select ARM_HEAVY_MB + select MST_IRQ help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same