From patchwork Fri Oct 2 13:34:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11813557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB19C112E for ; Fri, 2 Oct 2020 13:34:40 +0000 (UTC) Received: by mail.kernel.org (Postfix) id D5A1F22207; Fri, 2 Oct 2020 13:34:40 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pj1-f67.google.com (mail-pj1-f67.google.com [209.85.216.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C77A2220D for ; Fri, 2 Oct 2020 13:34:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="IgAPyLPh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C77A2220D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pj1-f67.google.com with SMTP id p21so839394pju.0 for ; Fri, 02 Oct 2020 06:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kzXjI15ZtttHCXeQ3n0cYLMP2xI/9tBvTIvB8MmIIvU=; b=IgAPyLPh0DLJmXt5xhnfVxXCfPj6O6jmDdV42a7glMLjKv2OtUZoRUkD4tSCN83ifi zmRzkcWRxhFbZ3Wsy0OqmseYh9ofBJhgwS2VBztlZEe33t138l0z8l4j5qY9QnoL/34X Iv1Te6dkP5J11PB089qvQYskoWblvll+96a5I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kzXjI15ZtttHCXeQ3n0cYLMP2xI/9tBvTIvB8MmIIvU=; b=hYPtLg/Ev4VgMP+Ym6pfeG/Vf04xiMt5nYRVN17ruTmRfMcuupp4IkC5KLO9GfJT7V hW0hcMgs552iqZl+vwskp0W3s6uKQSL7/YusBGZ4mqllAx6cSQK0mx/MNZ82LqGTZN8W YbdqXnBX+DckXIEO35brKkd8R6QE8wr0Dpg9lkyMJUDdkZES16t+iS3k2CQlTm+DAT/S hdvl/uOKVPrUdiOrYbkIzPNj+JaegpjNf9Wt3B2DIm8PP9VwoKqyTbV+Kbhk/+LkqP7A c4xp9TXie07NDlBqkhtQ6kJCVoqzRTBejwpga28559cuFZepEk0ewE6lzBq7Pg9veBHh 30NQ== X-Gm-Message-State: AOAM530M+SIv/9rswavYed9OE6Db9dFrPvAHiplMo2/yIdWLND2GW2vf TEUN/Nc0yqjJ9hKAp4x+RFuml9l5a0h+5A== X-Google-Smtp-Source: ABdhPJxzY+wQTKmU2f4036sr9ZNsSKMCauT7ECH8g+qEwbrTDG7ZWCcPqqlZJuV6LMMXhPkQPjIeTA== X-Received: by 2002:a17:90b:ecc:: with SMTP id gz12mr2723292pjb.219.1601645679700; Fri, 02 Oct 2020 06:34:39 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id k14sm1708219pjd.45.2020.10.02.06.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2020 06:34:39 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, mark-pk.tsai@mediatek.com, arnd@arndb.de, maz@kernel.org, Daniel Palmer Subject: [PATCH v2 2/5] ARM: mstar: Add interrupt controller to base dtsi Date: Fri, 2 Oct 2020 22:34:15 +0900 Message-Id: <20201002133418.2250277-3-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201002133418.2250277-1-daniel@0x0f.com> References: <20201002133418.2250277-1-daniel@0x0f.com> MIME-Version: 1.0 Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7 dtsi. All of the known SoCs have both and at the same place with their common IPs using the same interrupt lines. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..aec841b52ca4 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,25 @@ reboot { mask = <0x79>; }; + intc_fiq: interrupt-controller@201310 { + compatible = "mstar,mst-intc"; + reg = <0x201310 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <96 127>; + }; + + intc_irq: interrupt-controller@201350 { + compatible = "mstar,mst-intc"; + reg = <0x201350 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <32 95>; + mstar,intc-no-eoi; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>;