From patchwork Mon Nov 9 12:17:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11891437 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E90656A2 for ; Mon, 9 Nov 2020 12:18:35 +0000 (UTC) Received: by mail.kernel.org (Postfix) id E2FC120789; Mon, 9 Nov 2020 12:18:35 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E214207BC for ; Mon, 9 Nov 2020 12:18:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="I7miMOGh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E214207BC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pl1-f195.google.com with SMTP id f21so4652616plr.5 for ; Mon, 09 Nov 2020 04:18:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Rwi6JrG1Bh8jLLcugHVfWoJr8ivQS6AwCC3H82H1b4=; b=I7miMOGhEdT7J0NAhMTCfKP0YfrV8cuu7jT+qTWfzx/UnjvsFFumY3ebjucZ/PY2pX ky0LqVkrGZhe6mB1ixA2yMyu82I9qlME5l0pgUcbg1SSgGYKpmjCRQRm5SnNQf3K0Tg8 m15vf4PW2cnoTUbupzdVt1Vk6w6U7qPXghp8U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Rwi6JrG1Bh8jLLcugHVfWoJr8ivQS6AwCC3H82H1b4=; b=bCb+HM2aElllCZ+81knMQdPIkTUVUYmpQgAiBbTGDdc65deU1aF36pf7VTFPZCkUs+ MZn9yryuT/sT5ne1lmdx3xTyIxz8EFTbKcfOeguyE8D0A4hJ57EEwGS7LEiRFbFLmqLx W6zSQeTi8A6GjhRkpy0c8/adDBK3e+ngn792L9yxtq3U5D0KDvi5hkXf/aBvmqWSg/38 nKUpbvXgES5xXGQbz2anFgccQussHkvo5RTBMOxejA3NR/2dPvSJiU1UznYi1jCdhrtf P7MWwYcNZyD9rmLHhHi8cDVEccywfUwE+zQS2T43tFwIOg1iRwSiuPlgg6uFOLbKY4rT DgBQ== X-Gm-Message-State: AOAM530gxcpio1h0N8reOGgGP7yn4+mCgEUSznCH+YkxU5r0QglRhaNZ OtCJEjqRTFGj+hIp/eSZqi+nbP9ptGc4Pg== X-Google-Smtp-Source: ABdhPJwIBAsn/3BnPLGIM6HYZYH0I3QBpnJKi9ej88OHsCBcUhLvc1UBv92TWmV6pvx2zGKesCPqAg== X-Received: by 2002:a17:902:c411:b029:d7:dd6e:60b4 with SMTP id k17-20020a170902c411b02900d7dd6e60b4mr5462718plk.66.1604924314644; Mon, 09 Nov 2020 04:18:34 -0800 (PST) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id i123sm11425204pfc.13.2020.11.09.04.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2020 04:18:34 -0800 (PST) From: Daniel Palmer List-Id: To: soc@kernel.org, linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, maz@kernel.org, w@1wt.eu, Daniel Palmer Subject: [PATCH v3 4/5] ARM: mstar: Add gpio controller to MStar base dtsi Date: Mon, 9 Nov 2020 21:17:30 +0900 Message-Id: <20201109121731.1537580-5-daniel@0x0f.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201109121731.1537580-1-daniel@0x0f.com> References: <20201109121731.1537580-1-daniel@0x0f.com> MIME-Version: 1.0 The GPIO controller is at the same address in all of the currently known chips so create a node for it in the base dtsi. Some extra properties are needed to actually use it so disable it by default. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij --- arch/arm/boot/dts/mstar-v7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index f07880561e11..81369bc07f78 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -109,6 +109,16 @@ l3bridge: l3bridge@204400 { reg = <0x204400 0x200>; }; + gpio: gpio@207800 { + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "disabled"; + }; + pm_uart: uart@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>;