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[84.226.167.205]) by smtp.gmail.com with ESMTPSA id r11sm20977867wrm.26.2021.03.08.09.48.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:48:43 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: "Paul J. Murphy" , Daniele Alessandrelli , Dinh Nguyen , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [PATCH v2] arm64: defconfig: enable Intel's eASIC N5X SoCFPGA and Keem Bay SoC Date: Mon, 8 Mar 2021 18:48:24 +0100 Message-Id: <20210308174824.278372-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 From: Krzysztof Kozlowski Enable in defconfig two Intel ARM64 architectures: the eASIC N5X SoCFPGA and Keem Bay SoC. This allows compile coverage when building default config. For the N5X (and Agilex) enable also DesignWare SPI controller in MMIO. Signed-off-by: Krzysztof Kozlowski --- Hi Arnd, You asked me to check if all drivers are enabled for these platforms. In general the answer is yes. In particular: 1. Keem Bay is does not have much in upstream, but everything described in DTS is there, 2. N5X shares a lot with Agilex SoCFPGA which already (mostly) is supported. Changes since v1: 1. Enable also SPI_DW_MMIO --- arch/arm64/configs/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f633b771..9f9adcb8b0e9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -29,6 +29,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_PROFILING=y CONFIG_ARCH_ACTIONS=y CONFIG_ARCH_AGILEX=y +CONFIG_ARCH_N5X=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM2835=y @@ -41,6 +42,7 @@ CONFIG_ARCH_K3=y CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y +CONFIG_ARCH_KEEMBAY=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MVEBU=y @@ -465,6 +467,9 @@ CONFIG_SPI=y CONFIG_SPI_ARMADA_3700=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m CONFIG_SPI_FSL_LPSPI=y CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_NXP_FLEXSPI=y