| Message ID | 20210311152715.1317848-1-krzysztof.kozlowski@canonical.com (mailing list archive) |
|---|---|
| State | Queued, archived |
| Headers | show |
| Series | arm64 / clk: socfpga: simplifying, cleanups and compile testing | expand |
On 3/11/21 9:27 AM, Krzysztof Kozlowski wrote: > ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the > 32-bit ARM drivers to rely on new symbol. > > There is little point to share clock controller drivers between 32-bit > and 64-bit platforms because there will not be a generic image for both > of them. Therefore add a new Kconfig entry for building 32-bit clock > driverss, similar to one for 64-bit. This allows enabling compile > testing. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- > drivers/clk/socfpga/Kconfig | 6 +++++- > drivers/clk/socfpga/Makefile | 4 ++-- > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig > index b62ede8cad01..0cf16b894efb 100644 > --- a/drivers/clk/socfpga/Kconfig > +++ b/drivers/clk/socfpga/Kconfig > @@ -4,10 +4,14 @@ config CLK_INTEL_SOCFPGA > default ARCH_INTEL_SOCFPGA > help > Support for the clock controllers present on Intel SoCFPGA and eASIC > - devices like Stratix 10, Agilex and N5X eASIC. > + devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. > > if CLK_INTEL_SOCFPGA > > +config CLK_INTEL_SOCFPGA32 > + bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) > + default ARM && ARCH_INTEL_SOCFPGA > + > config CLK_INTEL_SOCFPGA64 > bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) > default ARM64 && ARCH_INTEL_SOCFPGA > diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile > index ebd3538d12de..e8dfce339c91 100644 > --- a/drivers/clk/socfpga/Makefile > +++ b/drivers/clk/socfpga/Makefile > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > -obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o > -obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o > +obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \ > + clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o > obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \ > clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ > clk-agilex.o > Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Quoting Krzysztof Kozlowski (2021-03-11 07:27:15) > ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the > 32-bit ARM drivers to rely on new symbol. > > There is little point to share clock controller drivers between 32-bit > and 64-bit platforms because there will not be a generic image for both > of them. Therefore add a new Kconfig entry for building 32-bit clock > driverss, similar to one for 64-bit. This allows enabling compile > testing. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index b62ede8cad01..0cf16b894efb 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -4,10 +4,14 @@ config CLK_INTEL_SOCFPGA default ARCH_INTEL_SOCFPGA help Support for the clock controllers present on Intel SoCFPGA and eASIC - devices like Stratix 10, Agilex and N5X eASIC. + devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. if CLK_INTEL_SOCFPGA +config CLK_INTEL_SOCFPGA32 + bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) + default ARM && ARCH_INTEL_SOCFPGA + config CLK_INTEL_SOCFPGA64 bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) default ARM64 && ARCH_INTEL_SOCFPGA diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index ebd3538d12de..e8dfce339c91 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o -obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o +obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \ + clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \ clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ clk-agilex.o
ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the 32-bit ARM drivers to rely on new symbol. There is little point to share clock controller drivers between 32-bit and 64-bit platforms because there will not be a generic image for both of them. Therefore add a new Kconfig entry for building 32-bit clock driverss, similar to one for 64-bit. This allows enabling compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- drivers/clk/socfpga/Kconfig | 6 +++++- drivers/clk/socfpga/Makefile | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-)