[RESEND#2,v4] MAINTAINERS: add polarfire rng, pci and clock drivers

Commit Message

Conor Dooley July 7, 2022, 2:20 p.m. UTC

Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.

Acked-by: Bjorn Helgaas <[e-mail]>
Acked-by: Stephen Boyd <[e-mail]>
Signed-off-by: Conor Dooley <[e-mail]>
---
Resending with +CC [e-mail]
It's a v4 because the other patches were applied/dropped.

 MAINTAINERS | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

[e-mail] July 8, 2022, 7:50 a.m. UTC | #1

Hello:

This patch was applied to soc/soc.git (arm/fixes)
by Arnd Bergmann <[e-mail]>:

On Thu, 7 Jul 2022 15:20:42 +0100 you wrote:
> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> Daire is the author of the clock & PCI drivers, so add him as a
> maintainer in place of Lewis.
> 
> Acked-by: Bjorn Helgaas <[e-mail]>
> Acked-by: Stephen Boyd <[e-mail]>
> Signed-off-by: Conor Dooley <[e-mail]>
> 
> [...]

Here is the summary with links:
  - [RESEND#2,v4] MAINTAINERS: add polarfire rng, pci and clock drivers
    https://git.kernel.org/soc/soc/c/2058dc831ff8

You are awesome, thank you!

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..01a7bfa49bdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17136,12 +17136,15 @@  N:	riscv
 K:	riscv
 
 RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
-M:	Lewis Hanly <[e-mail]>
 M:	Conor Dooley <[e-mail]>
+M:	Daire McNamara <[e-mail]>
 L:	[e-mail]
 S:	Supported
 F:	arch/riscv/boot/dts/microchip/
+F:	drivers/char/hw_random/mpfs-rng.c
+F:	drivers/clk/microchip/clk-mpfs.c
 F:	drivers/mailbox/mailbox-mpfs.c
+F:	drivers/pci/controller/pcie-microchip-host.c
 F:	drivers/soc/microchip/
 F:	include/soc/microchip/mpfs.h