From patchwork Wed Aug 10 14:02:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12940602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E1D2C00140 for ; Wed, 10 Aug 2022 14:03:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 6752CC433B5; Wed, 10 Aug 2022 14:03:54 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 65909C433C1; Wed, 10 Aug 2022 14:03:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 65909C433C1 Authentication-Results: smtp.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660140232; x=1691676232; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6wm8qFNBUY4i8KtmlFHnTGwoCmChYaNk0zbrd4k51PQ=; b=Op9Pr4xEIKq4D8iQfr0S6CAv23riv2gW8NzGb1cubViHaA8yXTg8kSDv sx0Kg75d2ZT9oJ2tmXiJFf+YN49YSLEm2uTgfdyF7lPR8DJaN2Udu/LwC YfUQG4XgJ8U3R0GZSEvPGhCKW+8WhemLFaAuS75kDi5AS0xIJJMQooopg KAqiEGaZlUw8XAYs/GhXOe06+EvsjUu7ZDRx7nn4umlNUBALk8XyhqOBx FDR1JjG3lDGyfQNYh1nRTCEpIGPqmzCRhguAzN3LRfGu8jCGrbOONUeCB 9uNS/sw5yqP/6VKO+XkQXywRZ4GVm5Wuyr2gjAZarvOA0nsqr+70rDTIl g==; X-IronPort-AV: E=Sophos;i="5.93,227,1654585200"; d="scan'208";a="108427959" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Aug 2022 07:03:48 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 10 Aug 2022 07:03:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Wed, 10 Aug 2022 07:03:45 -0700 From: Conor Dooley List-Id: To: , Daire McNamara CC: Mark Brown , Wolfram Sang , "Thierry Reding" , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Jassi Brar , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , "Arnd Bergmann" , Olof Johansson , Michael Turquette , Stephen Boyd , , , Conor Dooley , Marc Kleine-Budde Subject: [RESEND PATCH 1/2] MAINTAINERS: add PolarFire SoC dt bindings Date: Wed, 10 Aug 2022 15:02:43 +0100 Message-ID: <20220810140243.2685416-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220810140243.2685416-1-conor.dooley@microchip.com> References: <20220810140243.2685416-1-conor.dooley@microchip.com> MIME-Version: 1.0 So far when I added bindings for the platform I never added them to our MAINTAINERS entry. No time like the present to improve the coverage. CC: Mark Brown CC: Wolfram Sang CC: Thierry Reding CC: Uwe Kleine-König CC: Jassi Brar CC: Linus Walleij CC: Bartosz Golaszewski CC: Greg Kroah-Hartman CC: Arnd Bergmann CC: Olof Johansson CC: Michael Turquette CC: Stephen Boyd Suggested-by: Mark Brown Acked-by: Marc Kleine-Budde # for can Signed-off-by: Conor Dooley Acked-by: Uwe Kleine-König --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 868bbf31603d..fd0f10a110e7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17512,6 +17512,15 @@ M: Conor Dooley M: Daire McNamara L: linux-riscv@lists.infradead.org S: Supported +F: Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml +F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml +F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml F: arch/riscv/boot/dts/microchip/ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs.c