From patchwork Wed Oct 12 05:55:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 13004691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72798C4332F for ; Wed, 12 Oct 2022 05:56:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 486D8C433C1; Wed, 12 Oct 2022 05:56:50 +0000 (UTC) Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 07C3EC43146; Wed, 12 Oct 2022 05:56:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 07C3EC43146 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=icenowy.me ARC-Seal: i=1; a=rsa-sha256; t=1665554196; cv=none; d=zohomail.com; s=zohoarc; b=l0ZmpSuYtDi5QJ4pEpBhr7XKkN0csdx3TsjI/rkXNMkDCfxSOMKOc6p7ehyG2Sh83LFEyqD8cEEH+qW9OMQ7ogKxxC90b7wtXWUTwMb7dtsSnBLsWJDM4xND+3q/1sOr7GEGD/1Tph85UBP/O6ju8CeN386uZfbRa3h7/Aw6xf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665554196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=rIOcS1OPdlQxTt3UA0JfYxANFs/SYjhsbkgEyI8apBw=; b=Xapiq/b1vGV+DAwjFxowYJFTrs13qbH26wU7VerY4LELeFBTpNr2X4yPt4je1GAy2vVFMl+FbfLs7nlJbYvHnK7LaoXFLPweM8Imb31ZgJApfOTefbbIN0NWrLhGrMeg8bLVkmOR8901i0SEQVRx6uVEWgVMFVHPMP2hK2w83xE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1665554196; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=rIOcS1OPdlQxTt3UA0JfYxANFs/SYjhsbkgEyI8apBw=; b=GuvsOp5UCB5oOJ+1hA2YY4cebeBu87m9yx/Ybv4VRq7OHcSm7+xr+W6450zgM1G3 Uue+ZV62u6eqrKEveNeiPltofpWU83iJ0XJNaJ3V2L8KVzYCeoWid/hQQaCRVuezt2f Yx89R9ultXnlVFRlO3geWpnllW3t0VdrVqrpg6Eo= Received: from edelgard.fodlan.icenowy.me (112.94.102.144 [112.94.102.144]) by mx.zohomail.com with SMTPS id 1665554195157378.470387366199; Tue, 11 Oct 2022 22:56:35 -0700 (PDT) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Andre Przywara List-Id: Cc: soc@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng , Rob Herring Subject: [PATCH v2 02/10] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY Date: Wed, 12 Oct 2022 13:55:54 +0800 Message-Id: <20221012055602.1544944-3-uwu@icenowy.me> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221012055602.1544944-1-uwu@icenowy.me> References: <20221012055602.1544944-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs, because it has only one OTG USB controller, no host-only OHCI/EHCI controllers. Add a binding document for it. Following the current situation of one YAML file per SoC, this one is based on allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits removed. (The same driver in Linux, phy-sun4i-usb, covers all these binding files now.) Signed-off-by: Icenowy Zheng Reviewed-by: Rob Herring Reviewed-by: Andre Przywara --- Changes in v2: - Clarify the relation with other phy-sun4i-usb bindings. - Added Rob's ACK. .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml new file mode 100644 index 000000000000..22ff8e0f2331 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner F1C100s USB PHY Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#phy-cells": + const: 1 + + compatible: + const: allwinner,suniv-f1c100s-usb-phy + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy_ctrl + + clocks: + maxItems: 1 + description: USB OTG PHY bus clock + + clock-names: + const: usb0_phy + + resets: + maxItems: 1 + description: USB OTG reset + + reset-names: + const: usb0_reset + + usb0_id_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG ID pin + + usb0_vbus_det-gpios: + maxItems: 1 + description: GPIO to the USB OTG VBUS detect pin + + usb0_vbus_power-supply: + description: Power supply to detect the USB OTG VBUS + + usb0_vbus-supply: + description: Regulator controlling USB OTG VBUS + +required: + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + - reg-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; + };