From patchwork Wed Oct 12 05:55:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 13004717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1829AC4332F for ; Wed, 12 Oct 2022 05:57:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 012E9C433C1; Wed, 12 Oct 2022 05:57:19 +0000 (UTC) Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 20E68C433D7; Wed, 12 Oct 2022 05:57:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 20E68C433D7 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=icenowy.me ARC-Seal: i=1; a=rsa-sha256; t=1665554228; cv=none; d=zohomail.com; s=zohoarc; b=Sh0fN5seShmABWmmPhLfq6HOJSM1Jbgjj9JIy+dUiN2MEFJw7jG9CQVV9yVo9HnB6JbVW6K/w3ciBvRtGUVVTIoLapCmemcMmEbzqVel4HYpDIBI9BNHVirdW2iVIQvDGQsNrBRx6uXquk+AcOHUcVcLx/JBGl8NH/AI2bJFOR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665554228; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ViIK05Q+GfR4lkwmGAJ30lw+1V3VdsMiq3fDv32+df0=; b=B9K71C7R5hKmW8ybqfb+0e1oVjNEYPAJ2kiYt6Dg+rzH6+j0bXa34Y9E04usjSNMgIybnC8rlW26Jpmmb3D6MdtQ4xkaiTZfMk342ZIT+jAtGT+MocXHGoEifXQTO0q9GXwwPwiawjRLvUcXefTQBwpOEMk8mFFrL/PUF595HJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1665554228; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=ViIK05Q+GfR4lkwmGAJ30lw+1V3VdsMiq3fDv32+df0=; b=PF0YG3n+Ilr0rEfoGwZl5t9ipBb0b+GYB/dv6guINw3aknqFOySWzPImgD8FuK8b o9DxMdygBwsiI4RYNHMTFaSXqQaL3SnjB2Yg/Vdbp9k5BE4Ooa+anX5G7aTLlQKocD7 zXgzRkeQYW8ofzYZzQ6+UFeD/2rnuuNqNZja1Ivw= Received: from edelgard.fodlan.icenowy.me (112.94.102.144 [112.94.102.144]) by mx.zohomail.com with SMTPS id 1665554226549388.7219000626267; Tue, 11 Oct 2022 22:57:06 -0700 (PDT) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Andre Przywara List-Id: Cc: soc@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v2 06/10] ARM: suniv: add USB-related device nodes Date: Wed, 12 Oct 2022 13:55:58 +0800 Message-Id: <20221012055602.1544944-7-uwu@icenowy.me> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221012055602.1544944-1-uwu@icenowy.me> References: <20221012055602.1544944-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External The suniv SoC has a USB OTG controller and a USB PHY like other Allwinner SoCs. Add their device tree node. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- No changes since v1. arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b..a01541ba42c5 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -133,6 +133,32 @@ mmc1: mmc@1c10000 { #size-cells = <0>; }; + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>;