| Message ID | 20221106154826.6687-6-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | ARM: suniv: USB and PopStick board support | expand |
Dne nedelja, 06. november 2022 ob 16:48:20 CET je Andre Przywara napisal(a): > From: Icenowy Zheng <uwu@icenowy.me> > > The suniv SoC has a USB OTG controller and a USB PHY like other > Allwinner SoCs. > > Add their device tree node. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b..a01541ba42c5 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -133,6 +133,32 @@ mmc1: mmc@1c10000 { #size-cells = <0>; }; + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>;