diff mbox series

[v2,1/2] clk: nuvoton: Add clk-ma35d1.h for driver extern functions

Message ID 20230621031605.234149-2-ychuang570808@gmail.com (mailing list archive)
State Superseded
Headers show
Series clk: nuvoton: Use clk_parent_data instead and add a header file | expand

Commit Message

Jacky Huang June 21, 2023, 3:16 a.m. UTC 
From: Jacky Huang <ychuang3@nuvoton.com>

Moved the declaration of extern functions ma35d1_reg_clk_pll() and
ma35d1_reg_adc_clkdiv() from the .c files to the newly created header
file clk-ma35d1.h.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 drivers/clk/nuvoton/clk-ma35d1-divider.c |  7 ++--
 drivers/clk/nuvoton/clk-ma35d1-pll.c     |  5 ++-
 drivers/clk/nuvoton/clk-ma35d1.c         | 42 ++++++++++--------------
 drivers/clk/nuvoton/clk-ma35d1.h         | 18 ++++++++++
 4 files changed, 40 insertions(+), 32 deletions(-)
 create mode 100644 drivers/clk/nuvoton/clk-ma35d1.h

Comments

Arnd Bergmann June 21, 2023, 2:22 p.m. UTC | #1 
On Wed, Jun 21, 2023, at 05:16, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
>
> Moved the declaration of extern functions ma35d1_reg_clk_pll() and
> ma35d1_reg_adc_clkdiv() from the .c files to the newly created header
> file clk-ma35d1.h.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>


>  #define PLL_MAX_NUM		5
> @@ -20,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock);
>  #define REG_CLK_PWRCTL		0x00
>  #define REG_CLK_SYSCLK0		0x04
>  #define REG_CLK_SYSCLK1		0x08
> -#define REG_CLK_APBCLK0		0x0C
> +#define REG_CLK_APBCLK0		0x0c
>  #define REG_CLK_APBCLK1		0x10
>  #define REG_CLK_APBCLK2		0x14
>  #define REG_CLK_CLKSEL0		0x18
> -#define REG_CLK_CLKSEL1		0x1C
> +#define REG_CLK_CLKSEL1		0x1c
>  #define REG_CLK_CLKSEL2		0x20
>  #define REG_CLK_CLKSEL3		0x24
>  #define REG_CLK_CLKSEL4		0x28
> -#define REG_CLK_CLKDIV0		0x2C
> +#define REG_CLK_CLKDIV0		0x2c
>  #define REG_CLK_CLKDIV1		0x30
>  #define REG_CLK_CLKDIV2		0x34
>  #define REG_CLK_CLKDIV3		0x38
> -#define REG_CLK_CLKDIV4		0x3C
> +#define REG_CLK_CLKDIV4		0x3c
>  #define REG_CLK_CLKOCTL		0x40
>  #define REG_CLK_STATUS		0x50
>  #define REG_CLK_PLL0CTL0	0x60

This part of the patch does not relate to the decription, it
looks like a minor cleanup that should be a separate patch.

The actual change looks good and required, but I can't apply it
if it's mixed with unrelated changes like this.

    Arnd
Jacky Huang June 22, 2023, 1:42 a.m. UTC | #2 
On 2023/6/21 下午 10:22, Arnd Bergmann wrote:
> On Wed, Jun 21, 2023, at 05:16, Jacky Huang wrote:
>> From: Jacky Huang <ychuang3@nuvoton.com>
>>
>> Moved the declaration of extern functions ma35d1_reg_clk_pll() and
>> ma35d1_reg_adc_clkdiv() from the .c files to the newly created header
>> file clk-ma35d1.h.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>
>>   #define PLL_MAX_NUM		5
>> @@ -20,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock);
>>   #define REG_CLK_PWRCTL		0x00
>>   #define REG_CLK_SYSCLK0		0x04
>>   #define REG_CLK_SYSCLK1		0x08
>> -#define REG_CLK_APBCLK0		0x0C
>> +#define REG_CLK_APBCLK0		0x0c
>>   #define REG_CLK_APBCLK1		0x10
>>   #define REG_CLK_APBCLK2		0x14
>>   #define REG_CLK_CLKSEL0		0x18
>> -#define REG_CLK_CLKSEL1		0x1C
>> +#define REG_CLK_CLKSEL1		0x1c
>>   #define REG_CLK_CLKSEL2		0x20
>>   #define REG_CLK_CLKSEL3		0x24
>>   #define REG_CLK_CLKSEL4		0x28
>> -#define REG_CLK_CLKDIV0		0x2C
>> +#define REG_CLK_CLKDIV0		0x2c
>>   #define REG_CLK_CLKDIV1		0x30
>>   #define REG_CLK_CLKDIV2		0x34
>>   #define REG_CLK_CLKDIV3		0x38
>> -#define REG_CLK_CLKDIV4		0x3C
>> +#define REG_CLK_CLKDIV4		0x3c
>>   #define REG_CLK_CLKOCTL		0x40
>>   #define REG_CLK_STATUS		0x50
>>   #define REG_CLK_PLL0CTL0	0x60
> This part of the patch does not relate to the decription, it
> looks like a minor cleanup that should be a separate patch.
>
> The actual change looks good and required, but I can't apply it
> if it's mixed with unrelated changes like this.
>
>      Arnd

Dear Arnd,


Thanks for the advice.

I will extract the unrelated parts from this patch and create another 
patch for them.


Best Regards,

Jacky Huang
Arnd Bergmann June 22, 2023, 10:10 a.m. UTC | #3 
On Thu, Jun 22, 2023, at 03:42, Jacky Huang wrote:
> On 2023/6/21 下午 10:22, Arnd Bergmann wrote:
>
> I will extract the unrelated parts from this patch and create another 
> patch for them.
>

Ok, sounds good. It would be great to still get this today or tomorrow
though, as the merge window probably opens on Monday and I want to
have the tree in a good state before I send my pull request to Linus.

     Arnd
diff mbox series

Patch

diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c
index 0c2bed47909a..bb8c23d2b895 100644
--- a/drivers/clk/nuvoton/clk-ma35d1-divider.c
+++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c
@@ -9,6 +9,8 @@ 
 #include <linux/regmap.h>
 #include <linux/spinlock.h>
 
+#include "clk-ma35d1.h"
+
 struct ma35d1_adc_clk_div {
 	struct clk_hw hw;
 	void __iomem *reg;
@@ -20,11 +22,6 @@  struct ma35d1_adc_clk_div {
 	spinlock_t *lock;
 };
 
-struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
-				     struct clk_hw *parent_hw, spinlock_t *lock,
-				     unsigned long flags, void __iomem *reg,
-				     u8 shift, u8 width, u32 mask_bit);
-
 static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)
 {
 	return container_of(_hw, struct ma35d1_adc_clk_div, hw);
diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c
index e4c9f94e6796..ff3fb8b87c24 100644
--- a/drivers/clk/nuvoton/clk-ma35d1-pll.c
+++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c
@@ -15,6 +15,8 @@ 
 #include <linux/units.h>
 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
 
+#include "clk-ma35d1.h"
+
 /* PLL frequency limits */
 #define PLL_FREF_MAX_FREQ	(200 * HZ_PER_MHZ)
 #define PLL_FREF_MIN_FREQ	(1 * HZ_PER_MHZ)
@@ -71,9 +73,6 @@  struct ma35d1_clk_pll {
 	void __iomem *ctl2_base;
 };
 
-struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name,
-				  struct clk_hw *parent_hw, void __iomem *base);
-
 static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw)
 {
 	return container_of(_hw, struct ma35d1_clk_pll, hw);
diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
index 297b11585f00..733750dda0f4 100644
--- a/drivers/clk/nuvoton/clk-ma35d1.c
+++ b/drivers/clk/nuvoton/clk-ma35d1.c
@@ -12,6 +12,8 @@ 
 #include <linux/spinlock.h>
 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
 
+#include "clk-ma35d1.h"
+
 static DEFINE_SPINLOCK(ma35d1_lock);
 
 #define PLL_MAX_NUM		5
@@ -20,19 +22,19 @@  static DEFINE_SPINLOCK(ma35d1_lock);
 #define REG_CLK_PWRCTL		0x00
 #define REG_CLK_SYSCLK0		0x04
 #define REG_CLK_SYSCLK1		0x08
-#define REG_CLK_APBCLK0		0x0C
+#define REG_CLK_APBCLK0		0x0c
 #define REG_CLK_APBCLK1		0x10
 #define REG_CLK_APBCLK2		0x14
 #define REG_CLK_CLKSEL0		0x18
-#define REG_CLK_CLKSEL1		0x1C
+#define REG_CLK_CLKSEL1		0x1c
 #define REG_CLK_CLKSEL2		0x20
 #define REG_CLK_CLKSEL3		0x24
 #define REG_CLK_CLKSEL4		0x28
-#define REG_CLK_CLKDIV0		0x2C
+#define REG_CLK_CLKDIV0		0x2c
 #define REG_CLK_CLKDIV1		0x30
 #define REG_CLK_CLKDIV2		0x34
 #define REG_CLK_CLKDIV3		0x38
-#define REG_CLK_CLKDIV4		0x3C
+#define REG_CLK_CLKDIV4		0x3c
 #define REG_CLK_CLKOCTL		0x40
 #define REG_CLK_STATUS		0x50
 #define REG_CLK_PLL0CTL0	0x60
@@ -42,32 +44,24 @@  static DEFINE_SPINLOCK(ma35d1_lock);
 #define REG_CLK_PLL3CTL0	0x90
 #define REG_CLK_PLL3CTL1	0x94
 #define REG_CLK_PLL3CTL2	0x98
-#define REG_CLK_PLL4CTL0	0xA0
-#define REG_CLK_PLL4CTL1	0xA4
-#define REG_CLK_PLL4CTL2	0xA8
-#define REG_CLK_PLL5CTL0	0xB0
-#define REG_CLK_PLL5CTL1	0xB4
-#define REG_CLK_PLL5CTL2	0xB8
-#define REG_CLK_CLKDCTL		0xC0
-#define REG_CLK_CLKDSTS		0xC4
-#define REG_CLK_CDUPB		0xC8
-#define REG_CLK_CDLOWB		0xCC
-#define REG_CLK_CKFLTRCTL	0xD0
-#define REG_CLK_TESTCLK		0xF0
+#define REG_CLK_PLL4CTL0	0xa0
+#define REG_CLK_PLL4CTL1	0xa4
+#define REG_CLK_PLL4CTL2	0xa8
+#define REG_CLK_PLL5CTL0	0xb0
+#define REG_CLK_PLL5CTL1	0xb4
+#define REG_CLK_PLL5CTL2	0xb8
+#define REG_CLK_CLKDCTL		0xc0
+#define REG_CLK_CLKDSTS		0xc4
+#define REG_CLK_CDUPB		0xc8
+#define REG_CLK_CDLOWB		0xcc
+#define REG_CLK_CKFLTRCTL	0xd0
+#define REG_CLK_TESTCLK		0xf0
 #define REG_CLK_PLLCTL		0x40
 
 #define PLL_MODE_INT            0
 #define PLL_MODE_FRAC           1
 #define PLL_MODE_SS             2
 
-struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode,
-				  const char *name, struct clk_hw *parent_hw,
-				  void __iomem *base);
-struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
-				     struct clk_hw *hw, spinlock_t *lock,
-				     unsigned long flags, void __iomem *reg,
-				     u8 shift, u8 width, u32 mask_bit);
-
 static const struct clk_parent_data ca35clk_sel_clks[] = {
 	{ .index = 0 },  /* HXT */
 	{ .index = 1 },  /* CAPLL */
diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h
new file mode 100644
index 000000000000..3adee440f60a
--- /dev/null
+++ b/drivers/clk/nuvoton/clk-ma35d1.h
@@ -0,0 +1,18 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Nuvoton Technology Corp.
+ * Author: Chi-Fang Li <cfli0@nuvoton.com>
+ */
+
+#ifndef __DRV_CLK_NUVOTON_MA35D1_H
+#define __DRV_CLK_NUVOTON_MA35D1_H
+
+struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name,
+				  struct clk_hw *parent_hw, void __iomem *base);
+
+struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
+				     struct clk_hw *parent_hw, spinlock_t *lock,
+				     unsigned long flags, void __iomem *reg,
+				     u8 shift, u8 width, u32 mask_bit);
+
+#endif /* __DRV_CLK_NUVOTON_MA35D1_H */