From patchwork Fri Jun 23 20:30:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13291058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AB30EB64DD for ; Fri, 23 Jun 2023 20:37:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 50220C433CC; Fri, 23 Jun 2023 20:37:56 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 0A41AC433C0; Fri, 23 Jun 2023 20:37:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 0A41AC433C0 Authentication-Results: smtp.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552671; x=1719088671; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gvnR65uyKMk5CUoToEoiuPKzluNwCII060FV6LYqd6M=; b=2YCwkfr9Qdad90uhxd4YkDucjrXNq9cr9phSCslIOZ8eJnot7WobEIht udzIZ9wPgg1Ru8K1AApJRNw9NpxDAV3uf+1Yb9afnzKbYZjqseqiB8dxh FTvoq+ysS3ubs/o6OfigMuj82WEjOyHr5WiaJn6QkopZ4Advsddg9CP+V dPKqKqwa6xRtLHiaXP5z/QzKHLcuILMKr3E6inAX8dvsTkCerL1UGuJbx SdSmiiSayTvgjCukzh5MNlclgpcrgbl//SdIkgeGTaRKmgeKZSdUPUy90 ycXpuMW/YfAr6cFbjEIrev0GFNmmiFkn78qwB2dt3tKNSrjB3UQ5CFHBx A==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="158362329" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:37:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:37:48 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:37:21 -0700 From: Varshini Rajendran List-Id: To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 13/45] dt-bindings: atmel-sysreg: add bindings for sam9x7 Date: Sat, 24 Jun 2023 02:00:24 +0530 Message-ID: <20230623203056.689705-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Add RAM controller, shutdown controller & SFR DT bindings. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index ab1b352344ae..1e7349987d77 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,7 @@ PIT Timer required properties: shared across all System Controller members. PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or "microchip,sam9x7-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,6 +31,7 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", + "microchip,sam9x7-ddramc", "microchip,sama7g5-uddrc" - reg: Should contain registers location and length @@ -89,7 +90,7 @@ SHDWC SAMA5D2-Compatible Shutdown Controller required properties: - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or - "microchip,sama7g5-shdwc" + "microchip,sama7g5-shdwc" or "microchip,sam9x7-shdwc" - reg: should contain registers location and length - clocks: phandle to input clock. - #address-cells: should be one. The cell is the wake-up input index. @@ -156,7 +157,7 @@ required properties: - compatible: Should be "atmel,-sfr", "syscon" or "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". - It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x60-sfr" or "microchip,sam9x7-sfr", "syscon". - reg: Should contain registers location and length sfr@f0038000 {