From patchwork Thu Aug 3 22:42:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13340965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB7CBC00528 for ; Thu, 3 Aug 2023 22:43:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 8E213C433B6; Thu, 3 Aug 2023 22:43:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 94961C433CB; Thu, 3 Aug 2023 22:43:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691102587; bh=mkgjslj3UqmAoWtd2vZdQ4Vowszqgwhuroo4KSgo6cU=; h=From:Date:Subject:References:In-Reply-To:List-Id:To:Cc:From; b=Ue2/2BrPWwdvX5MfXhdFS9TPQVdPVFovIcMhMAIpkiy9PxrUxe5Gthxa11lRkZ+Z/ suw/MuQ9R5AV/kKuCel2LV9T4MdZuDNplh3sUAVPg2VTydAw6905v3bv1OKlijDZYr HzHwVUw9tG0gZXIjE5BiqPG9+D2Yd9MEVjuD4w6fqdMbvvZsklGNVsifqvRbivo+Fu PXAAjC8+zKWONkBLNK8nSc5b/dXWsCKvXGAt5r7sk+WMRQA7H7s6/vuA7T31vekuuT 8bOzzUehhX7rM8bKEC9yFKOsBufla4IGaS8fMFt/wViKG/s32IdckqOrOrp2bu7x6B MHedWr/MTf4MQ== Received: (nullmailer pid 3693752 invoked by uid 1000); Thu, 03 Aug 2023 22:42:55 -0000 From: Rob Herring Date: Thu, 03 Aug 2023 16:42:41 -0600 Subject: [PATCH v2 01/23] ARM: l2x0: Add explicit includes for init and types MIME-Version: 1.0 Message-Id: <20230803-dt-header-cleanups-for-soc-v2-1-d8de2cc88bff@kernel.org> References: <20230803-dt-header-cleanups-for-soc-v2-0-d8de2cc88bff@kernel.org> In-Reply-To: <20230803-dt-header-cleanups-for-soc-v2-0-d8de2cc88bff@kernel.org> List-Id: To: soc@kernel.org, Patrice Chotard , Tsahee Zidenberg , Antoine Tenart , Jisheng Zhang , Sebastian Hesselbarth , Andrew Lunn , Gregory Clement , Jean-Marie Verdun , Nick Hawkins , Lubomir Rintel , Linus Walleij , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Heiko Stuebner , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Viresh Kumar , Shiraz Has him , Stuart Yoder , Laurentiu Tudor , Jay Fang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Cristian Marussi , Shawn Guo , Sascha Hauer , Fabio Estevam , Matthias Brugger , AngeloGioacchino Del Regno , Florian Fainelli , Dinh Nguyen , Thierry Reding , Jonathan Hunter , Michal Simek , Joel Stanley , Andrew Jeffery , Ulf Hansson , Li Yang , Qiang Zhao Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-mediatek@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-pm@vger.kernel.org X-Mailer: b4 0.13-dev The cache-l2x0.h header uses u32 type and the __init and __iomem attributes, so it should have explicit includes for those. Signed-off-by: Rob Herring --- arch/arm/include/asm/hardware/cache-l2x0.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index a6d4ee86ba54..5a7ee70f561c 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -9,6 +9,8 @@ #define __ASM_ARM_HARDWARE_L2X0_H #include +#include +#include #define L2X0_CACHE_ID 0x000 #define L2X0_CACHE_TYPE 0x004