[v3,02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings

Commit Message

Peter Griffin Oct. 11, 2023, 6:48 p.m. UTC

Provide dt-schema documentation for Google gs101 SoC clock controller.
Currently this adds support for cmu_top, cmu_misc and cmu_apm.

Signed-off-by: Peter Griffin <[e-mail]>
---
 .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
 include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
 2 files changed, 357 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
 create mode 100644 include/dt-bindings/clock/google,gs101.h

Comments

William McVicker Oct. 11, 2023, 9:48 p.m. UTC | #1

On 10/11/2023, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> 
> Signed-off-by: Peter Griffin <[e-mail]>

Tested-by: Will McVicker <[e-mail]>

Thanks,
Will

> ---
>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <[e-mail]>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-misc
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +            - description: Misc bus clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_cmu_misc_bus
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-apm
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock controller node for CMU_TOP
> +  - |
> +    #include <dt-bindings/clock/google,gs101.h>
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +
> +        cmu_top: clock-controller@1e080000 {
> +            compatible = "google,gs101-cmu-top";
> +            reg = <0x0 0x1e080000 0x8000>;
> +            #clock-cells = <1>;
> +            clocks = <&ext_24_5m>;
> +            clock-names = "oscclk";
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> new file mode 100644
> index 000000000000..7765ba68f734
> --- /dev/null
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <[e-mail]>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL		1
> +#define CLK_FOUT_SHARED1_PLL		2
> +#define CLK_FOUT_SHARED2_PLL		3
> +#define CLK_FOUT_SHARED3_PLL		4
> +#define CLK_FOUT_SPARE_PLL		5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL		6
> +#define CLK_MOUT_SHARED1_PLL		7
> +#define CLK_MOUT_SHARED2_PLL		8
> +#define CLK_MOUT_SHARED3_PLL		9
> +#define CLK_MOUT_SPARE_PLL		10
> +#define CLK_MOUT_BUS0_BUS		11
> +#define CLK_MOUT_CMU_BOOST		12
> +#define CLK_MOUT_BUS1_BUS		13
> +#define CLK_MOUT_BUS2_BUS		14
> +#define CLK_MOUT_CORE_BUS		15
> +#define CLK_MOUT_EH_BUS			16
> +#define CLK_MOUT_CPUCL2_SWITCH		17
> +#define CLK_MOUT_CPUCL1_SWITCH		18
> +#define CLK_MOUT_CPUCL0_SWITCH		19
> +#define CLK_MOUT_CPUCL0_DBG		20
> +#define CLK_MOUT_CMU_HPM		21
> +#define CLK_MOUT_G3D_SWITCH		22
> +#define CLK_MOUT_G3D_GLB		23
> +#define CLK_MOUT_DPU_BUS		24
> +#define CLK_MOUT_DISP_BUS		25
> +#define CLK_MOUT_G2D_G2D		26
> +#define CLK_MOUT_G2D_MSCL		27
> +#define CLK_MOUT_HSI0_USB31DRD		28
> +#define CLK_MOUT_HSI0_BUS		29
> +#define CLK_MOUT_HSI0_DPGTC		30
> +#define CLK_MOUT_HSI0_USBDPDGB		31
> +#define CLK_MOUT_HSI1_BUS		32
> +#define CLK_MOUT_HSI1_PCIE		33
> +#define CLK_MOUT_HSI2_BUS		34
> +#define CLK_MOUT_HSI2_PCIE		35
> +#define CLK_MOUT_HSI2_UFS_EMBD		36
> +#define CLK_MOUT_HSI2_MMC_CARD		37
> +#define CLK_MOUT_CSIS			38
> +#define CLK_MOUT_PDP_BUS		39
> +#define CLK_MOUT_PDP_VRA		40
> +#define CLK_MOUT_IPP_BUS		41
> +#define CLK_MOUT_G3AA			42
> +#define CLK_MOUT_ITP			43
> +#define CLK_MOUT_DNS_BUS		44
> +#define CLK_MOUT_TNR_BUS		45
> +#define CLK_MOUT_MCSC_ITSC		46
> +#define CLK_MOUT_MCSC_MCSC		47
> +#define CLK_MOUT_GDC_SCSC		48
> +#define CLK_MOUT_GDC_GDC0		49
> +#define CLK_MOUT_GDC_GDC1		50
> +#define CLK_MOUT_MFC_MFC		51
> +#define CLK_MOUT_MIF_SWITCH		52
> +#define CLK_MOUT_MIF_BUS		53
> +#define CLK_MOUT_MISC_BUS		54
> +#define CLK_MOUT_MISC_SSS		55
> +#define CLK_MOUT_PERIC0_IP		56
> +#define CLK_MOUT_PERIC0_BUS		57
> +#define CLK_MOUT_PERIC1_IP		58
> +#define CLK_MOUT_PERIC1_BUS		59
> +#define CLK_MOUT_TPU_TPU		60
> +#define CLK_MOUT_TPU_TPUCTL		61
> +#define CLK_MOUT_TPU_BUS		62
> +#define CLK_MOUT_TPU_UART		63
> +#define CLK_MOUT_TPU_HPM		64
> +#define CLK_MOUT_BO_BUS			65
> +#define CLK_MOUT_G3D_BUSD		66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3		67
> +#define CLK_DOUT_SHARED0_DIV2		68
> +#define CLK_DOUT_SHARED0_DIV4		69
> +#define CLK_DOUT_SHARED0_DIV5		70
> +#define CLK_DOUT_SHARED1_DIV3		71
> +#define CLK_DOUT_SHARED1_DIV2		72
> +#define CLK_DOUT_SHARED1_DIV4		73
> +#define CLK_DOUT_SHARED2_DIV2		74
> +#define CLK_DOUT_SHARED3_DIV2		75
> +#define CLK_DOUT_BUS0_BUS		76
> +#define CLK_DOUT_CMU_BOOST		77
> +#define CLK_DOUT_BUS1_BUS		78
> +#define CLK_DOUT_BUS2_BUS		79
> +#define CLK_DOUT_CORE_BUS		80
> +#define CLK_DOUT_EH_BUS			81
> +#define CLK_DOUT_CPUCL2_SWITCH		82
> +#define CLK_DOUT_CPUCL1_SWITCH		83
> +#define CLK_DOUT_CPUCL0_SWITCH		84
> +#define CLK_DOUT_CPUCL0_DBG		85
> +#define CLK_DOUT_CMU_HPM		86
> +#define CLK_DOUT_G3D_SWITCH		87
> +#define CLK_DOUT_G3D_GLB		88
> +#define CLK_DOUT_DPU_BUS		89
> +#define CLK_DOUT_DISP_BUS		90
> +#define CLK_DOUT_G2D_G2D		91
> +#define CLK_DOUT_G2D_MSCL		92
> +#define CLK_DOUT_HSI0_USB31DRD		93
> +#define CLK_DOUT_HSI0_BUS		94
> +#define CLK_DOUT_HSI0_DPGTC		95
> +#define CLK_DOUT_HSI0_USBDPDGB		96
> +#define CLK_DOUT_HSI1_BUS		97
> +#define CLK_DOUT_HSI1_PCIE		98
> +#define CLK_DOUT_HSI2_BUS		100
> +#define CLK_DOUT_HSI2_PCIE		101
> +#define CLK_DOUT_HSI2_UFS_EMBD		102
> +#define CLK_DOUT_HSI2_MMC_CARD		103
> +#define CLK_DOUT_CSIS			104
> +#define CLK_DOUT_PDP_BUS		105
> +#define CLK_DOUT_PDP_VRA		106
> +#define CLK_DOUT_IPP_BUS		107
> +#define CLK_DOUT_G3AA			108
> +#define CLK_DOUT_ITP			109
> +#define CLK_DOUT_DNS_BUS		110
> +#define CLK_DOUT_TNR_BUS		111
> +#define CLK_DOUT_MCSC_ITSC		112
> +#define CLK_DOUT_MCSC_MCSC		113
> +#define CLK_DOUT_GDC_SCSC		114
> +#define CLK_DOUT_GDC_GDC0		115
> +#define CLK_DOUT_GDC_GDC1		116
> +#define CLK_DOUT_MFC_MFC		117
> +#define CLK_DOUT_MIF_BUS		118
> +#define CLK_DOUT_MISC_BUS		119
> +#define CLK_DOUT_MISC_SSS		120
> +#define CLK_DOUT_PERIC0_BUS		121
> +#define CLK_DOUT_PERIC0_IP		122
> +#define CLK_DOUT_PERIC1_BUS		123
> +#define CLK_DOUT_PERIC1_IP		124
> +#define CLK_DOUT_TPU_TPU		125
> +#define CLK_DOUT_TPU_TPUCTL		126
> +#define CLK_DOUT_TPU_BUS		127
> +#define CLK_DOUT_TPU_UART		128
> +#define CLK_DOUT_TPU_HPM		129
> +#define CLK_DOUT_BO_BUS			130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS		131
> +#define CLK_GOUT_BUS1_BUS		132
> +#define CLK_GOUT_BUS2_BUS		133
> +#define CLK_GOUT_CORE_BUS		134
> +#define CLK_GOUT_EH_BUS			135
> +#define CLK_GOUT_CPUCL2_SWITCH		136
> +#define CLK_GOUT_CPUCL1_SWITCH		137
> +#define CLK_GOUT_CPUCL0_SWITCH		138
> +#define CLK_GOUT_CPUCL0_DBG		139
> +#define CLK_GOUT_CMU_HPM		140
> +#define CLK_GOUT_G3D_SWITCH		141
> +#define CLK_GOUT_G3D_GLB		142
> +#define CLK_GOUT_DPU_BUS		143
> +#define CLK_GOUT_DISP_BUS		144
> +#define CLK_GOUT_G2D_G2D		145
> +#define CLK_GOUT_G2D_MSCL		146
> +#define CLK_GOUT_HSI0_USB31DRD		147
> +#define CLK_GOUT_HSI0_BUS		148
> +#define CLK_GOUT_HSI0_DPGTC		149
> +#define CLK_GOUT_HSI0_USBDPDGB		150
> +#define CLK_GOUT_HSI1_BUS		151
> +#define CLK_GOUT_HSI1_PCIE		152
> +#define CLK_GOUT_HSI2_BUS		153
> +#define CLK_GOUT_HSI2_PCIE		154
> +#define CLK_GOUT_HSI2_UFS_EMBD		155
> +#define CLK_GOUT_HSI2_MMC_CARD		156
> +#define CLK_GOUT_CSIS			157
> +#define CLK_GOUT_PDP_BUS		158
> +#define CLK_GOUT_PDP_VRA		159
> +#define CLK_GOUT_IPP_BUS		160
> +#define CLK_GOUT_G3AA			161
> +#define CLK_GOUT_ITP			162
> +#define CLK_GOUT_DNS_BUS		163
> +#define CLK_GOUT_TNR_BUS		164
> +#define CLK_GOUT_MCSC_ITSC		165
> +#define CLK_GOUT_MCSC_MCSC		166
> +#define CLK_GOUT_GDC_SCSC		167
> +#define CLK_GOUT_GDC_GDC0		168
> +#define CLK_GOUT_GDC_GDC1		169
> +#define CLK_GOUT_MFC_MFC		170
> +#define CLK_GOUT_MIF_SWITCH		171
> +#define CLK_GOUT_MIF_BUS		172
> +#define CLK_GOUT_MISC_BUS		173
> +#define CLK_GOUT_MISC_SSS		174
> +#define CLK_GOUT_PERIC0_BUS		175
> +#define CLK_GOUT_PERIC0_IP		176
> +#define CLK_GOUT_PERIC1_BUS		177
> +#define CLK_GOUT_PERIC1_IP		178
> +#define CLK_GOUT_TPU_TPU		179
> +#define CLK_GOUT_TPU_TPUCTL		180
> +#define CLK_GOUT_TPU_BUS		181
> +#define CLK_GOUT_TPU_UART		182
> +#define CLK_GOUT_TPU_HPM		183
> +#define CLK_GOUT_BO_BUS			184
> +#define CLK_GOUT_CMU_BOOST		185
> +
> +/* CMU_APM */
> +
> +#define CLK_MOUT_APM_FUNC					1
> +#define CLK_MOUT_APM_FUNCSRC					2
> +#define CLK_DOUT_APM_BOOST					3
> +#define CLK_DOUT_APM_USI0_UART					4
> +#define CLK_DOUT_APM_USI0_USI					5
> +#define CLK_DOUT_APM_USI1_UART					6
> +#define CLK_GOUT_APM_FUNC					7
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK	8
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK	9
> +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK		10
> +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK		11
> +#define CLK_APM_PLL_DIV2_APM					12
> +#define CLK_APM_PLL_DIV4_APM					13
> +#define CLK_APM_PLL_DIV16_APM					14
> +
> +/* CMU_MISC */
> +
> +#define CLK_MOUT_MISC_BUS_USER					1
> +#define CLK_MOUT_MISC_SSS_USER					2
> +#define CLK_DOUT_MISC_BUSP					3
> +#define CLK_DOUT_MISC_GIC					4
> +#define CLK_GOUT_MISC_PCLK					5
> +#define CLK_GOUT_MISC_SYSREG_PCLK				6
> +#define CLK_GOUT_MISC_WDT_CLUSTER0				7
> +#define CLK_GOUT_MISC_WDT_CLUSTER1				8
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> -- 
> 2.42.0.655.g421f12c284-goog
>

Sam Protsenko Oct. 11, 2023, 10:55 p.m. UTC | #2

On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin <[e-mail]> wrote:
>
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>
> Signed-off-by: Peter Griffin <[e-mail]>
> ---

Reviewed-by: Sam Protsenko <[e-mail]>

>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <[e-mail]>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-misc
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +            - description: Misc bus clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_cmu_misc_bus
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-apm
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +required:
> +  - compatible
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock controller node for CMU_TOP
> +  - |
> +    #include <dt-bindings/clock/google,gs101.h>
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <1>;
> +
> +        cmu_top: clock-controller@1e080000 {
> +            compatible = "google,gs101-cmu-top";
> +            reg = <0x0 0x1e080000 0x8000>;
> +            #clock-cells = <1>;
> +            clocks = <&ext_24_5m>;
> +            clock-names = "oscclk";
> +        };
> +    };
> +
> +...
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> new file mode 100644
> index 000000000000..7765ba68f734
> --- /dev/null
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -0,0 +1,232 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2023 Linaro Ltd.
> + * Author: Peter Griffin <[e-mail]>
> + *
> + * Device Tree binding constants for Google gs101 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
> +
> +/* CMU_TOP PLL*/
> +#define CLK_FOUT_SHARED0_PLL           1
> +#define CLK_FOUT_SHARED1_PLL           2
> +#define CLK_FOUT_SHARED2_PLL           3
> +#define CLK_FOUT_SHARED3_PLL           4
> +#define CLK_FOUT_SPARE_PLL             5
> +
> +/* CMU_TOP MUX*/
> +#define CLK_MOUT_SHARED0_PLL           6
> +#define CLK_MOUT_SHARED1_PLL           7
> +#define CLK_MOUT_SHARED2_PLL           8
> +#define CLK_MOUT_SHARED3_PLL           9
> +#define CLK_MOUT_SPARE_PLL             10
> +#define CLK_MOUT_BUS0_BUS              11
> +#define CLK_MOUT_CMU_BOOST             12
> +#define CLK_MOUT_BUS1_BUS              13
> +#define CLK_MOUT_BUS2_BUS              14
> +#define CLK_MOUT_CORE_BUS              15
> +#define CLK_MOUT_EH_BUS                        16
> +#define CLK_MOUT_CPUCL2_SWITCH         17
> +#define CLK_MOUT_CPUCL1_SWITCH         18
> +#define CLK_MOUT_CPUCL0_SWITCH         19
> +#define CLK_MOUT_CPUCL0_DBG            20
> +#define CLK_MOUT_CMU_HPM               21
> +#define CLK_MOUT_G3D_SWITCH            22
> +#define CLK_MOUT_G3D_GLB               23
> +#define CLK_MOUT_DPU_BUS               24
> +#define CLK_MOUT_DISP_BUS              25
> +#define CLK_MOUT_G2D_G2D               26
> +#define CLK_MOUT_G2D_MSCL              27
> +#define CLK_MOUT_HSI0_USB31DRD         28
> +#define CLK_MOUT_HSI0_BUS              29
> +#define CLK_MOUT_HSI0_DPGTC            30
> +#define CLK_MOUT_HSI0_USBDPDGB         31
> +#define CLK_MOUT_HSI1_BUS              32
> +#define CLK_MOUT_HSI1_PCIE             33
> +#define CLK_MOUT_HSI2_BUS              34
> +#define CLK_MOUT_HSI2_PCIE             35
> +#define CLK_MOUT_HSI2_UFS_EMBD         36
> +#define CLK_MOUT_HSI2_MMC_CARD         37
> +#define CLK_MOUT_CSIS                  38
> +#define CLK_MOUT_PDP_BUS               39
> +#define CLK_MOUT_PDP_VRA               40
> +#define CLK_MOUT_IPP_BUS               41
> +#define CLK_MOUT_G3AA                  42
> +#define CLK_MOUT_ITP                   43
> +#define CLK_MOUT_DNS_BUS               44
> +#define CLK_MOUT_TNR_BUS               45
> +#define CLK_MOUT_MCSC_ITSC             46
> +#define CLK_MOUT_MCSC_MCSC             47
> +#define CLK_MOUT_GDC_SCSC              48
> +#define CLK_MOUT_GDC_GDC0              49
> +#define CLK_MOUT_GDC_GDC1              50
> +#define CLK_MOUT_MFC_MFC               51
> +#define CLK_MOUT_MIF_SWITCH            52
> +#define CLK_MOUT_MIF_BUS               53
> +#define CLK_MOUT_MISC_BUS              54
> +#define CLK_MOUT_MISC_SSS              55
> +#define CLK_MOUT_PERIC0_IP             56
> +#define CLK_MOUT_PERIC0_BUS            57
> +#define CLK_MOUT_PERIC1_IP             58
> +#define CLK_MOUT_PERIC1_BUS            59
> +#define CLK_MOUT_TPU_TPU               60
> +#define CLK_MOUT_TPU_TPUCTL            61
> +#define CLK_MOUT_TPU_BUS               62
> +#define CLK_MOUT_TPU_UART              63
> +#define CLK_MOUT_TPU_HPM               64
> +#define CLK_MOUT_BO_BUS                        65
> +#define CLK_MOUT_G3D_BUSD              66
> +
> +/* CMU_TOP Dividers*/
> +#define CLK_DOUT_SHARED0_DIV3          67
> +#define CLK_DOUT_SHARED0_DIV2          68
> +#define CLK_DOUT_SHARED0_DIV4          69
> +#define CLK_DOUT_SHARED0_DIV5          70
> +#define CLK_DOUT_SHARED1_DIV3          71
> +#define CLK_DOUT_SHARED1_DIV2          72
> +#define CLK_DOUT_SHARED1_DIV4          73
> +#define CLK_DOUT_SHARED2_DIV2          74
> +#define CLK_DOUT_SHARED3_DIV2          75
> +#define CLK_DOUT_BUS0_BUS              76
> +#define CLK_DOUT_CMU_BOOST             77
> +#define CLK_DOUT_BUS1_BUS              78
> +#define CLK_DOUT_BUS2_BUS              79
> +#define CLK_DOUT_CORE_BUS              80
> +#define CLK_DOUT_EH_BUS                        81
> +#define CLK_DOUT_CPUCL2_SWITCH         82
> +#define CLK_DOUT_CPUCL1_SWITCH         83
> +#define CLK_DOUT_CPUCL0_SWITCH         84
> +#define CLK_DOUT_CPUCL0_DBG            85
> +#define CLK_DOUT_CMU_HPM               86
> +#define CLK_DOUT_G3D_SWITCH            87
> +#define CLK_DOUT_G3D_GLB               88
> +#define CLK_DOUT_DPU_BUS               89
> +#define CLK_DOUT_DISP_BUS              90
> +#define CLK_DOUT_G2D_G2D               91
> +#define CLK_DOUT_G2D_MSCL              92
> +#define CLK_DOUT_HSI0_USB31DRD         93
> +#define CLK_DOUT_HSI0_BUS              94
> +#define CLK_DOUT_HSI0_DPGTC            95
> +#define CLK_DOUT_HSI0_USBDPDGB         96
> +#define CLK_DOUT_HSI1_BUS              97
> +#define CLK_DOUT_HSI1_PCIE             98
> +#define CLK_DOUT_HSI2_BUS              100
> +#define CLK_DOUT_HSI2_PCIE             101
> +#define CLK_DOUT_HSI2_UFS_EMBD         102
> +#define CLK_DOUT_HSI2_MMC_CARD         103
> +#define CLK_DOUT_CSIS                  104
> +#define CLK_DOUT_PDP_BUS               105
> +#define CLK_DOUT_PDP_VRA               106
> +#define CLK_DOUT_IPP_BUS               107
> +#define CLK_DOUT_G3AA                  108
> +#define CLK_DOUT_ITP                   109
> +#define CLK_DOUT_DNS_BUS               110
> +#define CLK_DOUT_TNR_BUS               111
> +#define CLK_DOUT_MCSC_ITSC             112
> +#define CLK_DOUT_MCSC_MCSC             113
> +#define CLK_DOUT_GDC_SCSC              114
> +#define CLK_DOUT_GDC_GDC0              115
> +#define CLK_DOUT_GDC_GDC1              116
> +#define CLK_DOUT_MFC_MFC               117
> +#define CLK_DOUT_MIF_BUS               118
> +#define CLK_DOUT_MISC_BUS              119
> +#define CLK_DOUT_MISC_SSS              120
> +#define CLK_DOUT_PERIC0_BUS            121
> +#define CLK_DOUT_PERIC0_IP             122
> +#define CLK_DOUT_PERIC1_BUS            123
> +#define CLK_DOUT_PERIC1_IP             124
> +#define CLK_DOUT_TPU_TPU               125
> +#define CLK_DOUT_TPU_TPUCTL            126
> +#define CLK_DOUT_TPU_BUS               127
> +#define CLK_DOUT_TPU_UART              128
> +#define CLK_DOUT_TPU_HPM               129
> +#define CLK_DOUT_BO_BUS                        130
> +
> +/* CMU_TOP Gates*/
> +#define CLK_GOUT_BUS0_BUS              131
> +#define CLK_GOUT_BUS1_BUS              132
> +#define CLK_GOUT_BUS2_BUS              133
> +#define CLK_GOUT_CORE_BUS              134
> +#define CLK_GOUT_EH_BUS                        135
> +#define CLK_GOUT_CPUCL2_SWITCH         136
> +#define CLK_GOUT_CPUCL1_SWITCH         137
> +#define CLK_GOUT_CPUCL0_SWITCH         138
> +#define CLK_GOUT_CPUCL0_DBG            139
> +#define CLK_GOUT_CMU_HPM               140
> +#define CLK_GOUT_G3D_SWITCH            141
> +#define CLK_GOUT_G3D_GLB               142
> +#define CLK_GOUT_DPU_BUS               143
> +#define CLK_GOUT_DISP_BUS              144
> +#define CLK_GOUT_G2D_G2D               145
> +#define CLK_GOUT_G2D_MSCL              146
> +#define CLK_GOUT_HSI0_USB31DRD         147
> +#define CLK_GOUT_HSI0_BUS              148
> +#define CLK_GOUT_HSI0_DPGTC            149
> +#define CLK_GOUT_HSI0_USBDPDGB         150
> +#define CLK_GOUT_HSI1_BUS              151
> +#define CLK_GOUT_HSI1_PCIE             152
> +#define CLK_GOUT_HSI2_BUS              153
> +#define CLK_GOUT_HSI2_PCIE             154
> +#define CLK_GOUT_HSI2_UFS_EMBD         155
> +#define CLK_GOUT_HSI2_MMC_CARD         156
> +#define CLK_GOUT_CSIS                  157
> +#define CLK_GOUT_PDP_BUS               158
> +#define CLK_GOUT_PDP_VRA               159
> +#define CLK_GOUT_IPP_BUS               160
> +#define CLK_GOUT_G3AA                  161
> +#define CLK_GOUT_ITP                   162
> +#define CLK_GOUT_DNS_BUS               163
> +#define CLK_GOUT_TNR_BUS               164
> +#define CLK_GOUT_MCSC_ITSC             165
> +#define CLK_GOUT_MCSC_MCSC             166
> +#define CLK_GOUT_GDC_SCSC              167
> +#define CLK_GOUT_GDC_GDC0              168
> +#define CLK_GOUT_GDC_GDC1              169
> +#define CLK_GOUT_MFC_MFC               170
> +#define CLK_GOUT_MIF_SWITCH            171
> +#define CLK_GOUT_MIF_BUS               172
> +#define CLK_GOUT_MISC_BUS              173
> +#define CLK_GOUT_MISC_SSS              174
> +#define CLK_GOUT_PERIC0_BUS            175
> +#define CLK_GOUT_PERIC0_IP             176
> +#define CLK_GOUT_PERIC1_BUS            177
> +#define CLK_GOUT_PERIC1_IP             178
> +#define CLK_GOUT_TPU_TPU               179
> +#define CLK_GOUT_TPU_TPUCTL            180
> +#define CLK_GOUT_TPU_BUS               181
> +#define CLK_GOUT_TPU_UART              182
> +#define CLK_GOUT_TPU_HPM               183
> +#define CLK_GOUT_BO_BUS                        184
> +#define CLK_GOUT_CMU_BOOST             185
> +
> +/* CMU_APM */
> +
> +#define CLK_MOUT_APM_FUNC                                      1
> +#define CLK_MOUT_APM_FUNCSRC                                   2
> +#define CLK_DOUT_APM_BOOST                                     3
> +#define CLK_DOUT_APM_USI0_UART                                 4
> +#define CLK_DOUT_APM_USI0_USI                                  5
> +#define CLK_DOUT_APM_USI1_UART                                 6
> +#define CLK_GOUT_APM_FUNC                                      7
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK       8
> +#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK   9
> +#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK                10
> +#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK             11
> +#define CLK_APM_PLL_DIV2_APM                                   12
> +#define CLK_APM_PLL_DIV4_APM                                   13
> +#define CLK_APM_PLL_DIV16_APM                                  14
> +
> +/* CMU_MISC */
> +
> +#define CLK_MOUT_MISC_BUS_USER                                 1
> +#define CLK_MOUT_MISC_SSS_USER                                 2
> +#define CLK_DOUT_MISC_BUSP                                     3
> +#define CLK_DOUT_MISC_GIC                                      4
> +#define CLK_GOUT_MISC_PCLK                                     5
> +#define CLK_GOUT_MISC_SYSREG_PCLK                              6
> +#define CLK_GOUT_MISC_WDT_CLUSTER0                             7
> +#define CLK_GOUT_MISC_WDT_CLUSTER1                             8
> +
> +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> --
> 2.42.0.655.g421f12c284-goog
>

Krzysztof Kozlowski Oct. 12, 2023, 6:07 a.m. UTC | #3

On 11/10/2023 23:48, William McVicker wrote:
> On 10/11/2023, Peter Griffin wrote:
>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>
>> Signed-off-by: Peter Griffin <[e-mail]>
> 
> Tested-by: Will McVicker <[e-mail]>

And how do you perform testing of a binding?

Best regards,
Krzysztof

Krzysztof Kozlowski Oct. 12, 2023, 6:11 a.m. UTC | #4

On 11/10/2023 20:48, Peter Griffin wrote:
> Provide dt-schema documentation for Google gs101 SoC clock controller.
> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> 
> Signed-off-by: Peter Griffin <[e-mail]>
> ---
>  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
>  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
>  2 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>  create mode 100644 include/dt-bindings/clock/google,gs101.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google GS101 SoC clock controller
> +
> +maintainers:
> +  - Peter Griffin <[e-mail]>
> +
> +description: |
> +  Google GS101 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. The root clock in that clock tree
> +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> +  clock in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks available for usage
> +  in clock consumer nodes are defined as preprocessor macros in
> +  'dt-bindings/clock/gs101.h' header.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +allOf:

No improvements here from v1.

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: google,gs101-cmu-top
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:

enum:
  - google,gs101-cmu-apm
  - google,gs101-cmu-misc


Best regards,
Krzysztof

Peter Griffin Oct. 12, 2023, 8:56 a.m. UTC | #5

Hi Krzysztof,

On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
<[e-mail]> wrote:
>
> On 11/10/2023 23:48, William McVicker wrote:
> > On 10/11/2023, Peter Griffin wrote:
> >> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>
> >> Signed-off-by: Peter Griffin <[e-mail]>
> >
> > Tested-by: Will McVicker <[e-mail]>
>
> And how do you perform testing of a binding?

I guess if William is using my script to build and flash the kernel it actually
runs the DTC checks as part of the build process.

See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44

regards,

Peter.

Krzysztof Kozlowski Oct. 12, 2023, 9:36 a.m. UTC | #6

On 12/10/2023 10:56, Peter Griffin wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> <[e-mail]> wrote:
>>
>> On 11/10/2023 23:48, William McVicker wrote:
>>> On 10/11/2023, Peter Griffin wrote:
>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>>>
>>>> Signed-off-by: Peter Griffin <[e-mail]>
>>>
>>> Tested-by: Will McVicker <[e-mail]>
>>
>> And how do you perform testing of a binding?
> 
> I guess if William is using my script to build and flash the kernel it actually
> runs the DTC checks as part of the build process.
> 
> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44

So it is a build test? We do not consider building as a test procedure,
otherwise I should add my and robots tested-by to many other patches.
Shall I consider other Tested-by tags here also as build-tested only?

Best regards,
Krzysztof

Peter Griffin Oct. 12, 2023, 10:15 a.m. UTC | #7

Hi Krzysztof,

Thanks for your review.

On Thu, 12 Oct 2023 at 07:11, Krzysztof Kozlowski
<[e-mail]> wrote:
>
> On 11/10/2023 20:48, Peter Griffin wrote:
> > Provide dt-schema documentation for Google gs101 SoC clock controller.
> > Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >
> > Signed-off-by: Peter Griffin <[e-mail]>
> > ---
> >  .../bindings/clock/google,gs101-clock.yaml    | 125 ++++++++++
> >  include/dt-bindings/clock/google,gs101.h      | 232 ++++++++++++++++++
> >  2 files changed, 357 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> >  create mode 100644 include/dt-bindings/clock/google,gs101.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > new file mode 100644
> > index 000000000000..f74494594b3b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > @@ -0,0 +1,125 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Google GS101 SoC clock controller
> > +
> > +maintainers:
> > +  - Peter Griffin <[e-mail]>
> > +
> > +description: |
> > +  Google GS101 clock controller is comprised of several CMU units, generating
> > +  clocks for different domains. Those CMU units are modeled as separate device
> > +  tree nodes, and might depend on each other. The root clock in that clock tree
> > +  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
> > +  clock in dts.
> > +
> > +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> > +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> > +
> > +  Each clock is assigned an identifier and client nodes can use this identifier
> > +  to specify the clock which they consume. All clocks available for usage
> > +  in clock consumer nodes are defined as preprocessor macros in
> > +  'dt-bindings/clock/gs101.h' header.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - google,gs101-cmu-top
> > +      - google,gs101-cmu-apm
> > +      - google,gs101-cmu-misc
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +allOf:
>
> No improvements here from v1.

Seems I missed the
"required:" go before "allOf:" comment here. Sorry about that I've fixed that
in v4.

Seems like a few other exynos clock yaml bindings need that fix to.

>
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: google,gs101-cmu-top
> > +
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: External reference clock (24.576 MHz)
> > +
> > +        clock-names:
> > +          items:
> > +            - const: oscclk
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
>
> enum:
>   - google,gs101-cmu-apm
>   - google,gs101-cmu-misc

Ok just to be clear, are you saying I should have it like this?

  - if:
      properties:
        compatible:
          contains:
            enum:
              - google,gs101-cmu-misc
              - google,gs101-cmu-apm

    then:
      properties:
        clocks:
          minItems: 1
          items:
            - description: External reference clock (24.576 MHz)
            - description: Misc bus clock (from CMU_TOP)

        clock-names:
          minItems: 1
          items:
            - const: oscclk
            - const: dout_cmu_misc_bus

Instead of a dedicated  'if: const <compatible> then: ' for each CMU?

If I'm wrong above would you been kind enough to elaborate a bit
more on what you want, as all this dt-schema yaml stuff is a bit new
for me

Many thanks,

Peter

Krzysztof Kozlowski Oct. 12, 2023, 10:20 a.m. UTC | #8

On 12/10/2023 12:15, Peter Griffin wrote:

>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: google,gs101-cmu-top
>>> +
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          items:
>>> +            - description: External reference clock (24.576 MHz)
>>> +
>>> +        clock-names:
>>> +          items:
>>> +            - const: oscclk
>>> +
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>
>> enum:
>>   - google,gs101-cmu-apm
>>   - google,gs101-cmu-misc
> 
> Ok just to be clear, are you saying I should have it like this?
> 
>   - if:
>       properties:
>         compatible:
>           contains:
>             enum:
>               - google,gs101-cmu-misc

No, my bad, I meant apm + google,gs101-cmu-top

>               - google,gs101-cmu-apm




Best regards,
Krzysztof

Peter Griffin Oct. 12, 2023, 10:39 a.m. UTC | #9

Hi Krzysztof

On Thu, 12 Oct 2023 at 11:20, Krzysztof Kozlowski
<[e-mail]> wrote:
>
> On 12/10/2023 12:15, Peter Griffin wrote:
>
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            const: google,gs101-cmu-top
> >>> +
> >>> +    then:
> >>> +      properties:
> >>> +        clocks:
> >>> +          items:
> >>> +            - description: External reference clock (24.576 MHz)
> >>> +
> >>> +        clock-names:
> >>> +          items:
> >>> +            - const: oscclk
> >>> +
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>
> >> enum:
> >>   - google,gs101-cmu-apm
> >>   - google,gs101-cmu-misc
> >
> > Ok just to be clear, are you saying I should have it like this?
> >
> >   - if:
> >       properties:
> >         compatible:
> >           contains:
> >             enum:
> >               - google,gs101-cmu-misc
>
> No, my bad, I meant apm + google,gs101-cmu-top
>
> >               - google,gs101-cmu-apm

Ah OK, yes that makes more sense. Thanks for the clarification :)

Peter.

Peter Griffin Oct. 12, 2023, 10:45 a.m. UTC | #10

Hi Krzysztof,

On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
<[e-mail]> wrote:
>
> On 12/10/2023 10:56, Peter Griffin wrote:
> > Hi Krzysztof,
> >
> > On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> > <[e-mail]> wrote:
> >>
> >> On 11/10/2023 23:48, William McVicker wrote:
> >>> On 10/11/2023, Peter Griffin wrote:
> >>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>>>
> >>>> Signed-off-by: Peter Griffin <[e-mail]>
> >>>
> >>> Tested-by: Will McVicker <[e-mail]>
> >>
> >> And how do you perform testing of a binding?
> >
> > I guess if William is using my script to build and flash the kernel it actually
> > runs the DTC checks as part of the build process.
> >
> > See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
>
> So it is a build test? We do not consider building as a test procedure,
> otherwise I should add my and robots tested-by to many other patches.

Ok so I should only add the Tested-by on the .c patches?

> Shall I consider other Tested-by tags here also as build-tested only?

No. William indicated here
https://lore.kernel.org/linux-arm-kernel/[e-mail]/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
that he booted it on his Oriole device.

Peter.

Krzysztof Kozlowski Oct. 12, 2023, 11:33 a.m. UTC | #11

On 12/10/2023 12:45, Peter Griffin wrote:
> Hi Krzysztof,
> 
> On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
> <[e-mail]> wrote:
>>
>> On 12/10/2023 10:56, Peter Griffin wrote:
>>> Hi Krzysztof,
>>>
>>> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
>>> <[e-mail]> wrote:
>>>>
>>>> On 11/10/2023 23:48, William McVicker wrote:
>>>>> On 10/11/2023, Peter Griffin wrote:
>>>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
>>>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
>>>>>>
>>>>>> Signed-off-by: Peter Griffin <[e-mail]>
>>>>>
>>>>> Tested-by: Will McVicker <[e-mail]>
>>>>
>>>> And how do you perform testing of a binding?
>>>
>>> I guess if William is using my script to build and flash the kernel it actually
>>> runs the DTC checks as part of the build process.
>>>
>>> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
>>
>> So it is a build test? We do not consider building as a test procedure,
>> otherwise I should add my and robots tested-by to many other patches.
> 
> Ok so I should only add the Tested-by on the .c patches?

In my opinion, if someone performs only build testing, it is not a
testing. You cannot test the bindings other way than build testing, at
least I do not know such way. Of course other code like C or DTS affects
hardware so it can be tested.

> 
>> Shall I consider other Tested-by tags here also as build-tested only?
> 
> No. William indicated here
> https://lore.kernel.org/linux-arm-kernel/[e-mail]/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
> that he booted it on his Oriole device.


OK, I was just a bit confused.

Best regards,
Krzysztof

William McVicker Oct. 12, 2023, 4:41 p.m. UTC | #12

Hi Krzysztof,

On 10/12/2023, Krzysztof Kozlowski wrote:
> On 12/10/2023 12:45, Peter Griffin wrote:
> > Hi Krzysztof,
> > 
> > On Thu, 12 Oct 2023 at 10:36, Krzysztof Kozlowski
> > <[e-mail]> wrote:
> >>
> >> On 12/10/2023 10:56, Peter Griffin wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Thu, 12 Oct 2023 at 07:07, Krzysztof Kozlowski
> >>> <[e-mail]> wrote:
> >>>>
> >>>> On 11/10/2023 23:48, William McVicker wrote:
> >>>>> On 10/11/2023, Peter Griffin wrote:
> >>>>>> Provide dt-schema documentation for Google gs101 SoC clock controller.
> >>>>>> Currently this adds support for cmu_top, cmu_misc and cmu_apm.
> >>>>>>
> >>>>>> Signed-off-by: Peter Griffin <[e-mail]>
> >>>>>
> >>>>> Tested-by: Will McVicker <[e-mail]>
> >>>>
> >>>> And how do you perform testing of a binding?
> >>>
> >>> I guess if William is using my script to build and flash the kernel it actually
> >>> runs the DTC checks as part of the build process.
> >>>
> >>> See https://git.codelinaro.org/linaro/googlelt/pixelscripts/-/blob/clo/main/buildp21upstream.sh#L44
> >>
> >> So it is a build test? We do not consider building as a test procedure,
> >> otherwise I should add my and robots tested-by to many other patches.
> > 
> > Ok so I should only add the Tested-by on the .c patches?
> 
> In my opinion, if someone performs only build testing, it is not a
> testing. You cannot test the bindings other way than build testing, at
> least I do not know such way. Of course other code like C or DTS affects
> hardware so it can be tested.

What additional testing beside building and booting do you prefer at this
stage? I put my Tested-by for this patch because it includes the google,gs101.h
header which is used by the DT and clock controller driver during boot. Maybe
I should have been more clear on what I tested in each patch instead of only
mentioning how I tested in the cover letter?

Sorry for the confusion.

Thanks,
Will

> 
> > 
> >> Shall I consider other Tested-by tags here also as build-tested only?
> > 
> > No. William indicated here
> > https://lore.kernel.org/linux-arm-kernel/[e-mail]/T/#mbd96a26b725d6c85eb4193de8cd70ff277bc728e
> > that he booted it on his Oriole device.
> 
> 
> OK, I was just a bit confused.
> 
> Best regards,
> Krzysztof
>

Stephen Boyd Oct. 12, 2023, 11:34 p.m. UTC | #13

Quoting Peter Griffin (2023-10-11 11:48:05)
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> new file mode 100644
> index 000000000000..f74494594b3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -0,0 +1,125 @@
[...]
> +properties:
> +  compatible:
> +    enum:
> +      - google,gs101-cmu-top
> +      - google,gs101-cmu-apm
> +      - google,gs101-cmu-misc
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 2

Can you remove clock-names from the binding and simply use the index of
the clocks property? That means less string comparisons in the kernel.
I'm not sure if other samsung clk drivers are doing this though so maybe
clock-names is preferred for historical reasons.

Patch

diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
new file mode 100644
index 000000000000..f74494594b3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -0,0 +1,125 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 SoC clock controller
+
+maintainers:
+  - Peter Griffin <[e-mail]>
+
+description: |
+  Google GS101 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that clock tree
+  is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
+  clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'dt-bindings/clock/gs101.h' header.
+
+properties:
+  compatible:
+    enum:
+      - google,gs101-cmu-top
+      - google,gs101-cmu-apm
+      - google,gs101-cmu-misc
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-misc
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: Misc bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_misc_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-apm
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_TOP
+  - |
+    #include <dt-bindings/clock/google,gs101.h>
+    soc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        cmu_top: clock-controller@1e080000 {
+            compatible = "google,gs101-cmu-top";
+            reg = <0x0 0x1e080000 0x8000>;
+            #clock-cells = <1>;
+            clocks = <&ext_24_5m>;
+            clock-names = "oscclk";
+        };
+    };
+
+...
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
new file mode 100644
index 000000000000..7765ba68f734
--- /dev/null
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -0,0 +1,232 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <[e-mail]>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL*/
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SPARE_PLL		5
+
+/* CMU_TOP MUX*/
+#define CLK_MOUT_SHARED0_PLL		6
+#define CLK_MOUT_SHARED1_PLL		7
+#define CLK_MOUT_SHARED2_PLL		8
+#define CLK_MOUT_SHARED3_PLL		9
+#define CLK_MOUT_SPARE_PLL		10
+#define CLK_MOUT_BUS0_BUS		11
+#define CLK_MOUT_CMU_BOOST		12
+#define CLK_MOUT_BUS1_BUS		13
+#define CLK_MOUT_BUS2_BUS		14
+#define CLK_MOUT_CORE_BUS		15
+#define CLK_MOUT_EH_BUS			16
+#define CLK_MOUT_CPUCL2_SWITCH		17
+#define CLK_MOUT_CPUCL1_SWITCH		18
+#define CLK_MOUT_CPUCL0_SWITCH		19
+#define CLK_MOUT_CPUCL0_DBG		20
+#define CLK_MOUT_CMU_HPM		21
+#define CLK_MOUT_G3D_SWITCH		22
+#define CLK_MOUT_G3D_GLB		23
+#define CLK_MOUT_DPU_BUS		24
+#define CLK_MOUT_DISP_BUS		25
+#define CLK_MOUT_G2D_G2D		26
+#define CLK_MOUT_G2D_MSCL		27
+#define CLK_MOUT_HSI0_USB31DRD		28
+#define CLK_MOUT_HSI0_BUS		29
+#define CLK_MOUT_HSI0_DPGTC		30
+#define CLK_MOUT_HSI0_USBDPDGB		31
+#define CLK_MOUT_HSI1_BUS		32
+#define CLK_MOUT_HSI1_PCIE		33
+#define CLK_MOUT_HSI2_BUS		34
+#define CLK_MOUT_HSI2_PCIE		35
+#define CLK_MOUT_HSI2_UFS_EMBD		36
+#define CLK_MOUT_HSI2_MMC_CARD		37
+#define CLK_MOUT_CSIS			38
+#define CLK_MOUT_PDP_BUS		39
+#define CLK_MOUT_PDP_VRA		40
+#define CLK_MOUT_IPP_BUS		41
+#define CLK_MOUT_G3AA			42
+#define CLK_MOUT_ITP			43
+#define CLK_MOUT_DNS_BUS		44
+#define CLK_MOUT_TNR_BUS		45
+#define CLK_MOUT_MCSC_ITSC		46
+#define CLK_MOUT_MCSC_MCSC		47
+#define CLK_MOUT_GDC_SCSC		48
+#define CLK_MOUT_GDC_GDC0		49
+#define CLK_MOUT_GDC_GDC1		50
+#define CLK_MOUT_MFC_MFC		51
+#define CLK_MOUT_MIF_SWITCH		52
+#define CLK_MOUT_MIF_BUS		53
+#define CLK_MOUT_MISC_BUS		54
+#define CLK_MOUT_MISC_SSS		55
+#define CLK_MOUT_PERIC0_IP		56
+#define CLK_MOUT_PERIC0_BUS		57
+#define CLK_MOUT_PERIC1_IP		58
+#define CLK_MOUT_PERIC1_BUS		59
+#define CLK_MOUT_TPU_TPU		60
+#define CLK_MOUT_TPU_TPUCTL		61
+#define CLK_MOUT_TPU_BUS		62
+#define CLK_MOUT_TPU_UART		63
+#define CLK_MOUT_TPU_HPM		64
+#define CLK_MOUT_BO_BUS			65
+#define CLK_MOUT_G3D_BUSD		66
+
+/* CMU_TOP Dividers*/
+#define CLK_DOUT_SHARED0_DIV3		67
+#define CLK_DOUT_SHARED0_DIV2		68
+#define CLK_DOUT_SHARED0_DIV4		69
+#define CLK_DOUT_SHARED0_DIV5		70
+#define CLK_DOUT_SHARED1_DIV3		71
+#define CLK_DOUT_SHARED1_DIV2		72
+#define CLK_DOUT_SHARED1_DIV4		73
+#define CLK_DOUT_SHARED2_DIV2		74
+#define CLK_DOUT_SHARED3_DIV2		75
+#define CLK_DOUT_BUS0_BUS		76
+#define CLK_DOUT_CMU_BOOST		77
+#define CLK_DOUT_BUS1_BUS		78
+#define CLK_DOUT_BUS2_BUS		79
+#define CLK_DOUT_CORE_BUS		80
+#define CLK_DOUT_EH_BUS			81
+#define CLK_DOUT_CPUCL2_SWITCH		82
+#define CLK_DOUT_CPUCL1_SWITCH		83
+#define CLK_DOUT_CPUCL0_SWITCH		84
+#define CLK_DOUT_CPUCL0_DBG		85
+#define CLK_DOUT_CMU_HPM		86
+#define CLK_DOUT_G3D_SWITCH		87
+#define CLK_DOUT_G3D_GLB		88
+#define CLK_DOUT_DPU_BUS		89
+#define CLK_DOUT_DISP_BUS		90
+#define CLK_DOUT_G2D_G2D		91
+#define CLK_DOUT_G2D_MSCL		92
+#define CLK_DOUT_HSI0_USB31DRD		93
+#define CLK_DOUT_HSI0_BUS		94
+#define CLK_DOUT_HSI0_DPGTC		95
+#define CLK_DOUT_HSI0_USBDPDGB		96
+#define CLK_DOUT_HSI1_BUS		97
+#define CLK_DOUT_HSI1_PCIE		98
+#define CLK_DOUT_HSI2_BUS		100
+#define CLK_DOUT_HSI2_PCIE		101
+#define CLK_DOUT_HSI2_UFS_EMBD		102
+#define CLK_DOUT_HSI2_MMC_CARD		103
+#define CLK_DOUT_CSIS			104
+#define CLK_DOUT_PDP_BUS		105
+#define CLK_DOUT_PDP_VRA		106
+#define CLK_DOUT_IPP_BUS		107
+#define CLK_DOUT_G3AA			108
+#define CLK_DOUT_ITP			109
+#define CLK_DOUT_DNS_BUS		110
+#define CLK_DOUT_TNR_BUS		111
+#define CLK_DOUT_MCSC_ITSC		112
+#define CLK_DOUT_MCSC_MCSC		113
+#define CLK_DOUT_GDC_SCSC		114
+#define CLK_DOUT_GDC_GDC0		115
+#define CLK_DOUT_GDC_GDC1		116
+#define CLK_DOUT_MFC_MFC		117
+#define CLK_DOUT_MIF_BUS		118
+#define CLK_DOUT_MISC_BUS		119
+#define CLK_DOUT_MISC_SSS		120
+#define CLK_DOUT_PERIC0_BUS		121
+#define CLK_DOUT_PERIC0_IP		122
+#define CLK_DOUT_PERIC1_BUS		123
+#define CLK_DOUT_PERIC1_IP		124
+#define CLK_DOUT_TPU_TPU		125
+#define CLK_DOUT_TPU_TPUCTL		126
+#define CLK_DOUT_TPU_BUS		127
+#define CLK_DOUT_TPU_UART		128
+#define CLK_DOUT_TPU_HPM		129
+#define CLK_DOUT_BO_BUS			130
+
+/* CMU_TOP Gates*/
+#define CLK_GOUT_BUS0_BUS		131
+#define CLK_GOUT_BUS1_BUS		132
+#define CLK_GOUT_BUS2_BUS		133
+#define CLK_GOUT_CORE_BUS		134
+#define CLK_GOUT_EH_BUS			135
+#define CLK_GOUT_CPUCL2_SWITCH		136
+#define CLK_GOUT_CPUCL1_SWITCH		137
+#define CLK_GOUT_CPUCL0_SWITCH		138
+#define CLK_GOUT_CPUCL0_DBG		139
+#define CLK_GOUT_CMU_HPM		140
+#define CLK_GOUT_G3D_SWITCH		141
+#define CLK_GOUT_G3D_GLB		142
+#define CLK_GOUT_DPU_BUS		143
+#define CLK_GOUT_DISP_BUS		144
+#define CLK_GOUT_G2D_G2D		145
+#define CLK_GOUT_G2D_MSCL		146
+#define CLK_GOUT_HSI0_USB31DRD		147
+#define CLK_GOUT_HSI0_BUS		148
+#define CLK_GOUT_HSI0_DPGTC		149
+#define CLK_GOUT_HSI0_USBDPDGB		150
+#define CLK_GOUT_HSI1_BUS		151
+#define CLK_GOUT_HSI1_PCIE		152
+#define CLK_GOUT_HSI2_BUS		153
+#define CLK_GOUT_HSI2_PCIE		154
+#define CLK_GOUT_HSI2_UFS_EMBD		155
+#define CLK_GOUT_HSI2_MMC_CARD		156
+#define CLK_GOUT_CSIS			157
+#define CLK_GOUT_PDP_BUS		158
+#define CLK_GOUT_PDP_VRA		159
+#define CLK_GOUT_IPP_BUS		160
+#define CLK_GOUT_G3AA			161
+#define CLK_GOUT_ITP			162
+#define CLK_GOUT_DNS_BUS		163
+#define CLK_GOUT_TNR_BUS		164
+#define CLK_GOUT_MCSC_ITSC		165
+#define CLK_GOUT_MCSC_MCSC		166
+#define CLK_GOUT_GDC_SCSC		167
+#define CLK_GOUT_GDC_GDC0		168
+#define CLK_GOUT_GDC_GDC1		169
+#define CLK_GOUT_MFC_MFC		170
+#define CLK_GOUT_MIF_SWITCH		171
+#define CLK_GOUT_MIF_BUS		172
+#define CLK_GOUT_MISC_BUS		173
+#define CLK_GOUT_MISC_SSS		174
+#define CLK_GOUT_PERIC0_BUS		175
+#define CLK_GOUT_PERIC0_IP		176
+#define CLK_GOUT_PERIC1_BUS		177
+#define CLK_GOUT_PERIC1_IP		178
+#define CLK_GOUT_TPU_TPU		179
+#define CLK_GOUT_TPU_TPUCTL		180
+#define CLK_GOUT_TPU_BUS		181
+#define CLK_GOUT_TPU_UART		182
+#define CLK_GOUT_TPU_HPM		183
+#define CLK_GOUT_BO_BUS			184
+#define CLK_GOUT_CMU_BOOST		185
+
+/* CMU_APM */
+
+#define CLK_MOUT_APM_FUNC					1
+#define CLK_MOUT_APM_FUNCSRC					2
+#define CLK_DOUT_APM_BOOST					3
+#define CLK_DOUT_APM_USI0_UART					4
+#define CLK_DOUT_APM_USI0_USI					5
+#define CLK_DOUT_APM_USI1_UART					6
+#define CLK_GOUT_APM_FUNC					7
+#define CLK_GOUT_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK	8
+#define CLK_GOUT_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK	9
+#define CLK_GOUT_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK		10
+#define CLK_GOUT_APM_UID_SYSREG_APM_IPCLKPORT_PCLK		11
+#define CLK_APM_PLL_DIV2_APM					12
+#define CLK_APM_PLL_DIV4_APM					13
+#define CLK_APM_PLL_DIV16_APM					14
+
+/* CMU_MISC */
+
+#define CLK_MOUT_MISC_BUS_USER					1
+#define CLK_MOUT_MISC_SSS_USER					2
+#define CLK_DOUT_MISC_BUSP					3
+#define CLK_DOUT_MISC_GIC					4
+#define CLK_GOUT_MISC_PCLK					5
+#define CLK_GOUT_MISC_SYSREG_PCLK				6
+#define CLK_GOUT_MISC_WDT_CLUSTER0				7
+#define CLK_GOUT_MISC_WDT_CLUSTER1				8
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */