From patchwork Mon Oct 23 02:12:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 13432274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D1BBC0032E for ; Mon, 23 Oct 2023 02:12:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 2F0CCC433CA; Mon, 23 Oct 2023 02:12:32 +0000 (UTC) Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by smtp.kernel.org (Postfix) with ESMTP id E5A6AC433C8; Mon, 23 Oct 2023 02:12:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org E5A6AC433C8 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=socionext.com Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 23 Oct 2023 11:12:28 +0900 Received: from mail.mfilter.local (mail-arc01.css.socionext.com [10.213.46.36]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 97CC52059034; Mon, 23 Oct 2023 11:12:28 +0900 (JST) Received: from kinkan2.css.socionext.com ([172.31.9.51]) by m-FILTER with ESMTP; Mon, 23 Oct 2023 11:12:28 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id E8626B1D40; Mon, 23 Oct 2023 11:12:27 +0900 (JST) From: Kunihiko Hayashi List-Id: To: soc@kernel.org, Arnd Bergmann Cc: Pierre Gondois , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 1/2] arm64: dts: Update cache properties for socionext Date: Mon, 23 Oct 2023 11:12:20 +0900 Message-Id: <20231023021221.2884828-2-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023021221.2884828-1-hayashi.kunihiko@socionext.com> References: <20231023021221.2884828-1-hayashi.kunihiko@socionext.com> MIME-Version: 1.0 From: Pierre Gondois The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Reviewed-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com Signed-off-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b071475..54e58d945fd7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272..18390cba2eda 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,12 @@ cpu3: cpu@101 { a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea42..56e037900818 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; };