| Message ID | 20231028155101.1039049-1-hch@lst.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 946bb33d330251966223f770f64885c79448b1a1 |
| Headers | show |
| Series | riscv: split cache ops out of dma-noncoherent.c | expand |
On Sat, Oct 28, 2023 at 05:51:01PM +0200, Christoph Hellwig wrote: > The cache ops are also used by the pmem code which is unconditionally > built into the kernel. Move them into a separate file that is built > based on the correct config option. > > Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Christoph Hellwig <hch@lst.de> This fixes two different sets of built warnings reported by Randy. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Sat, Oct 28, 2023 at 4:55 PM Christoph Hellwig <hch@lst.de> wrote: > > The cache ops are also used by the pmem code which is unconditionally > built into the kernel. Move them into a separate file that is built > based on the correct config option. > > Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/riscv/mm/Makefile | 1 + > arch/riscv/mm/cache-ops.c | 17 +++++++++++++++++ > arch/riscv/mm/dma-noncoherent.c | 15 --------------- > 3 files changed, 18 insertions(+), 15 deletions(-) > create mode 100644 arch/riscv/mm/cache-ops.c > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # On RZ/Five SMARC Cheers, Prabhakar > diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile > index 9c454f90fd3da2..3a4dfc8babcf8c 100644 > --- a/arch/riscv/mm/Makefile > +++ b/arch/riscv/mm/Makefile > @@ -36,3 +36,4 @@ endif > > obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o > obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o > +obj-$(CONFIG_RISCV_NONSTANDARD_CACHE_OPS) += cache-ops.o > diff --git a/arch/riscv/mm/cache-ops.c b/arch/riscv/mm/cache-ops.c > new file mode 100644 > index 00000000000000..a993ad11d0eca9 > --- /dev/null > +++ b/arch/riscv/mm/cache-ops.c > @@ -0,0 +1,17 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > + */ > + > +#include <asm/dma-noncoherent.h> > + > +struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init; > + > +void > +riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops) > +{ > + if (!ops) > + return; > + noncoherent_cache_ops = *ops; > +} > +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > index b76e7e192eb183..341bd6706b4c56 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -15,12 +15,6 @@ static bool noncoherent_supported __ro_after_init; > int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN; > EXPORT_SYMBOL_GPL(dma_cache_alignment); > > -struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init = { > - .wback = NULL, > - .inv = NULL, > - .wback_inv = NULL, > -}; > - > static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) > { > void *vaddr = phys_to_virt(paddr); > @@ -162,12 +156,3 @@ void __init riscv_set_dma_cache_alignment(void) > if (!noncoherent_supported) > dma_cache_alignment = 1; > } > - > -void riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops) > -{ > - if (!ops) > - return; > - > - noncoherent_cache_ops = *ops; > -} > -EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); > -- > 2.39.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Sat, 28 Oct 2023 17:51:01 +0200 you wrote: > The cache ops are also used by the pmem code which is unconditionally > built into the kernel. Move them into a separate file that is built > based on the correct config option. > > Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Christoph Hellwig <hch@lst.de> > > [...] Here is the summary with links: - riscv: split cache ops out of dma-noncoherent.c https://git.kernel.org/riscv/c/946bb33d3302 You are awesome, thank you!
Hello: This patch was applied to soc/soc.git (arm/fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Sat, 28 Oct 2023 17:51:01 +0200 you wrote: > The cache ops are also used by the pmem code which is unconditionally > built into the kernel. Move them into a separate file that is built > based on the correct config option. > > Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Christoph Hellwig <hch@lst.de> > > [...] Here is the summary with links: - riscv: split cache ops out of dma-noncoherent.c https://git.kernel.org/soc/soc/c/946bb33d3302 You are awesome, thank you!
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 9c454f90fd3da2..3a4dfc8babcf8c 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -36,3 +36,4 @@ endif obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o +obj-$(CONFIG_RISCV_NONSTANDARD_CACHE_OPS) += cache-ops.o diff --git a/arch/riscv/mm/cache-ops.c b/arch/riscv/mm/cache-ops.c new file mode 100644 index 00000000000000..a993ad11d0eca9 --- /dev/null +++ b/arch/riscv/mm/cache-ops.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include <asm/dma-noncoherent.h> + +struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init; + +void +riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops) +{ + if (!ops) + return; + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b76e7e192eb183..341bd6706b4c56 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -15,12 +15,6 @@ static bool noncoherent_supported __ro_after_init; int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN; EXPORT_SYMBOL_GPL(dma_cache_alignment); -struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init = { - .wback = NULL, - .inv = NULL, - .wback_inv = NULL, -}; - static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); @@ -162,12 +156,3 @@ void __init riscv_set_dma_cache_alignment(void) if (!noncoherent_supported) dma_cache_alignment = 1; } - -void riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops) -{ - if (!ops) - return; - - noncoherent_cache_ops = *ops; -} -EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);
The cache ops are also used by the pmem code which is unconditionally built into the kernel. Move them into a separate file that is built based on the correct config option. Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/mm/Makefile | 1 + arch/riscv/mm/cache-ops.c | 17 +++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 15 --------------- 3 files changed, 18 insertions(+), 15 deletions(-) create mode 100644 arch/riscv/mm/cache-ops.c