From patchwork Thu Dec 12 15:52:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 13905450 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80A2A217F46 for ; Thu, 12 Dec 2024 15:52:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018778; cv=none; b=SRgNF9IxB4iqPWXxxTCqmsR7ntvNL93maKaUgwJkA8kw+LCRxG57wuKmDKhwKnYv5N8IVSfZIJdwXxeTO44NnJvx979MIRyNvc/oyaR+LN9CzGRBKUTJVzWXj5g6D8wEjstaKSZUfRHi2+XzePN+WC7JCGmKKn4Ts7urXU/csRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734018778; c=relaxed/simple; bh=89PFqU35zhClTqon3B8nMOkbBmnqgNpCWz2KMIlwKCs=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C0qiVcgmfRVcWZOemHwCkWgBTp5Wgzi+/IbnQuY/7M2FnxKDLNUpTeRVrHbVdivejtcZ3dM3TWlIClIQgnW18/z5DCNmUnupC0230lonA6IwTBpyMN5MDKGzpCIGxEu7/XSG3uufLydcsZC2X2IhMb+P9K0LttWWSXMLNs/MfZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 12 Dec 2024 23:52:41 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 12 Dec 2024 23:52:41 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 1/6] dt-bindings: interrupt-controller: Refine size/interrupt-cell usage. Date: Thu, 12 Dec 2024 23:52:31 +0800 Message-ID: <20241212155237.848336-3-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241212155237.848336-1-kevin_chen@aspeedtech.com> References: <20241212155237.848336-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 1. Because size-cells is no need to use 2, modify to 1 for use. 2. Add minItems to 1 for interrupts for intc1. 3. Add 1 interrupt of intc1 example into yaml file. 4. Add intc1 sub-module of uart12 as example using the intc0 and intc1. --- .../aspeed,ast2700-intc.yaml | 60 +++++++++++++++---- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml index 55636d06a674..eadfbc45326b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml @@ -31,6 +31,7 @@ properties: type as defined in interrupt.txt in this directory. interrupts: + minItems: 1 maxItems: 6 description: | Depend to which INTC0 or INTC1 used. @@ -68,19 +69,52 @@ examples: #include bus { + #address-cells = <2>; + #size-cells = <1>; + + intc0: interrupt-controller@12100000 { + compatible = "simple-mfd"; + reg = <0 0x12100000 0x4000>; + ranges = <0x0 0x0 0x0 0x12100000 0x4000>; #address-cells = <2>; - #size-cells = <2>; - - interrupt-controller@12101b00 { - compatible = "aspeed,ast2700-intc-ic"; - reg = <0 0x12101b00 0 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - interrupts = , - , - , - , - , - ; + #size-cells = <1>; + + intc0_11: interrupt-controller@1b00 { + compatible = "aspeed,ast2700-intc-ic"; + reg = <0 0x12101b00 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + , + , + , + , + ; }; + }; + + intc1: interrupt-controller@14c18000 { + compatible = "simple-mfd"; + reg = <0 0x14c18000 0x400>; + ranges = <0x0 0x0 0x0 0x14c18000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + + intc1_4: interrupt-controller@140 { + compatible = "aspeed,ast2700-intc-ic"; + reg = <0x0 0x140 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x100>; + interrupts-extended = <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test; + }; };