| Message ID | 20250111171126.369502-1-andersson@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | d1181e342bff46837d93ca6534e0c8117856d92d |
| Headers | show |
| Series | [GIT,PULL] Qualcomm Arm32 DeviceTree updates for v6.14 | expand |
Hello: This pull request was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Sat, 11 Jan 2025 11:11:26 -0600 you wrote: > The following changes since commit 40384c840ea1944d7c5a392e8975ed088ecf0b37: > > Linux 6.13-rc1 (2024-12-01 14:28:56 -0800) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm32-for-6.14 > > [...] Here is the summary with links: - [GIT,PULL] Qualcomm Arm32 DeviceTree updates for v6.14 https://git.kernel.org/soc/soc/c/d1181e342bff You are awesome, thank you!
The following changes since commit 40384c840ea1944d7c5a392e8975ed088ecf0b37: Linux 6.13-rc1 (2024-12-01 14:28:56 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm32-for-6.14 for you to fetch changes up to e3bab40d5961453545ef39aeb5198d2e718c9693: ARM: dts: qcom: sdx55: Disable USB U1/U2 entry (2025-01-06 17:49:34 -0600) ---------------------------------------------------------------- Qualcomm Arm32 DeviceTree updates for v6.14 Describe the interconnect paths for PCIe EP controllers on SDX55 and SDX65. Disable USB U1/U2 entry to improve USB stability on the same. ---------------------------------------------------------------- Krishna chaitanya chundru (2): ARM: dts: qcom: sdx65: Add PCIe EP interconnect path ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect path Prashanth K (2): ARM: dts: qcom: sdx65: Disable USB U1/U2 entry ARM: dts: qcom: sdx55: Disable USB U1/U2 entry arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 7 +++++-- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-)