| Message ID | 878sda2dj0.fsf@microchip.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 38c419037abe6d5fd8df20569cd9b0262983902b |
| Headers | show
Return-Path: <SRS0=ULu1=CZ=microchip.com=Lars.Povlsen@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42FAF6CA for <patchwork-soc@patchwork.kernel.org>; Wed, 16 Sep 2020 10:59:20 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 3C35E2080C; Wed, 16 Sep 2020 10:59:20 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C98FD2076D; Wed, 16 Sep 2020 10:59:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NBzRuxeB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C98FD2076D Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=tempfail smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1600253960; x=1631789960; h=from:to:cc:subject:date:message-id:mime-version; bh=9AnX9Owbeq7YKtr3bmjW5mDPEDCAIdPDn9C4shVYP/I=; b=NBzRuxeBfMjAyVnO4FR8FxcvkLqckfgw2WqpXeIdsWbZzxzKHNzUtKTZ 84tKJVSaP1UzCscCELB0UUU5WvXwfco5SjmfqeYof6sHHQP5LsJo6tS4K Y9kATVupxn9ELIRn4yuCbKZ56GlrvSRCDaFv5I6cI2YAPc4Gy/YJA4LaK QAtCCzaxGlfvre5jJ4TOjW2bISIfhX+1cb2aF7/vSQ/fOBDcy5aFLwQjU PHMGzGhupzNvtqkMV06ZWz+hMe3JhROw3AexmhxOeuev5e+SDjQg3fRzN oH4jY29IdFoa1ooV0vUIbWriHCPqVlnzSTbH93l2hixJTpd8uLby/xHOX A==; IronPort-SDR: YL8khqUdgAeulZ5MFaj9DxTfNlADE8JrnZlVclI/YWwVse8HJQQGWudMYGLTgc2HG0HVctPw3+ 1NUQXPlu4VFmCtec6A/YLXhCB8sHuajOIW9C4gRziqmLQ2pAKHO2Hu/dizSdm48y5wA9HkZ5yA RtElREe8CdWbkkXpC7hfuBWzmmm1rFDASYnHQmcIvjvjtC32uHeO83LdmWw7C3eF5/OAi2bsxq fp6/A7Be+wnx+QOzUoB6+vQUyYKpZMOVOnMdO54Cn0X0blOa3wK0H0BGCXdFHB3nTRVXp91cD8 Vbo= X-IronPort-AV: E=Sophos;i="5.76,432,1592895600"; d="scan'208";a="91200839" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Sep 2020 03:59:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 16 Sep 2020 03:59:01 -0700 Received: from soft-dev10.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3 via Frontend Transport; Wed, 16 Sep 2020 03:58:59 -0700 User-agent: mu4e 1.2.0; emacs 26.3 From: Lars Povlsen <lars.povlsen@microchip.com> List-Id: <soc.lore.kernel.org> To: Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>, <arm@kernel.org>, <soc@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com>, "Microchip Linux Driver Support" <UNGLinuxDriver@microchip.com>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: [GIT PULL] ARM: sparx5: SoC for 5.9 Date: Wed, 16 Sep 2020 12:59:15 +0200 Message-ID: <878sda2dj0.fsf@microchip.com> MIME-Version: 1.0 Content-Type: text/plain |
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[GIT,PULL] ARM: sparx5: SoC for 5.9
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The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5: Linux 5.9-rc1 (2020-08-16 13:04:57 -0700) are available in the Git repository at: https://github.com/microchip-ung/linux-upstream.git tags/sparx5-dt-5.10 for you to fetch changes up to 5df50128050d01d300f28d9bca4dd89d6d24de3d: arm64: dts: sparx5: Add spi-nand devices (2020-09-16 11:39:51 +0200) ---------------------------------------------------------------- Sparx5 DT updates for Linux 5.10 - Add public repo to MAINTAINERS - Add SPI controller and devices - Add eMMC controller and devices - Add temperature sensor ---------------------------------------------------------------- Lars Povlsen (6): arm64: dts: sparx5: Add Sparx5 eMMC support arm64: dts: sparx5: Add hwmon temperature sensor MAINTAINERS: Add git tree for Sparx5 arm64: dts: sparx5: Add SPI controller and associated mmio-mux arm64: dts: sparx5: Add spi-nor support arm64: dts: sparx5: Add spi-nand devices MAINTAINERS | 1 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 81 ++++++++++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 53 ++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb134.dts | 1 + .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 32 +++++++++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++++++ arch/arm64/boot/dts/microchip/sparx5_pcb135.dts | 1 + .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 32 +++++++++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++++++ 10 files changed, 278 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi