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Tue, 3 Sep 2024 13:14:57 -0400 (EDT) From: Jiaxun Yang Date: Tue, 03 Sep 2024 18:14:35 +0100 Subject: [PATCH 2/3] MIPS: Rename mips_instruction type to workaround bindgen issue Precedence: bulk X-Mailing-List: linux-trace-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-mips-rust-v1-2-0fdf0b2fd58f@flygoat.com> References: <20240903-mips-rust-v1-0-0fdf0b2fd58f@flygoat.com> In-Reply-To: <20240903-mips-rust-v1-0-0fdf0b2fd58f@flygoat.com> To: Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Thomas Bogendoerfer , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Jonathan Corbet , Alex Shi , Yanteng Si , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, linux-mips@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6582; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=CIsXpNL4Xqbe4+3LwKSPPuuUUgffBKKKBhZHlqW00Cg=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTrLmztR2edEbzKcelDgmzRh5tFU2fd27y66MKPxq7+x 6yCNrdjO0pZGMS4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAib+4y/NMya+8+epvzINv7 btHfobmnhGV2FJqdzFU/UT1r6pH0rAhGhqUXrnoLvp13pdiOz6fiwZJ3P8O6l0ioVttlbWLKWWx zmRUA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 We have a union and a type both named after mips_instruction, rust bindgen is not happy with this kind of naming alias. Given that union mips_instruction is a part of UAPI, the only thing we can do is to rename mips_instruction type. Rename it as mips_insn, which is not conflicting with anything and fits the name of header. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/dsemul.h | 2 +- arch/mips/include/asm/inst.h | 6 +++--- arch/mips/kernel/ftrace.c | 2 +- arch/mips/kernel/kprobes.c | 2 +- arch/mips/math-emu/cp1emu.c | 18 +++++++++--------- arch/mips/math-emu/dsemul.c | 8 ++++---- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h index 08bfe8fa3b40..870597d6d1ad 100644 --- a/arch/mips/include/asm/dsemul.h +++ b/arch/mips/include/asm/dsemul.h @@ -34,7 +34,7 @@ struct task_struct; * * Return: Zero on success, negative if ir is a NOP, signal number on failure. */ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, +extern int mips_dsemul(struct pt_regs *regs, mips_insn ir, unsigned long branch_pc, unsigned long cont_pc); /** diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 2f98ced30263..0616b8eb7401 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -71,12 +71,12 @@ #define I_FMA_FFMT_SFT 0 #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007) -typedef unsigned int mips_instruction; +typedef unsigned int mips_insn; /* microMIPS instruction decode structure. Do NOT export!!! */ struct mm_decoded_insn { - mips_instruction insn; - mips_instruction next_insn; + mips_insn insn; + mips_insn next_insn; int pc_inc; int next_pc_inc; int micro_mips_mode; diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 8c401e42301c..153c9666a77c 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -248,7 +248,7 @@ int ftrace_disable_ftrace_graph_caller(void) #define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ #define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ -unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long +static long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long old_parent_ra, unsigned long parent_ra_addr, unsigned long fp) { unsigned long sp, ip, tmp; diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index dc39f5b3fb83..7a1b1c3674da 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -90,7 +90,7 @@ int arch_prepare_kprobe(struct kprobe *p) } if (copy_from_kernel_nofault(&prev_insn, p->addr - 1, - sizeof(mips_instruction)) == 0 && + sizeof(kprobe_opcode_t)) == 0 && insn_has_delayslot(prev_insn)) { pr_notice("Kprobes for branch delayslot are not supported\n"); ret = -EINVAL; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 265bc57819df..bcd6a6f0034c 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -43,10 +43,10 @@ /* Function which emulates a floating point instruction. */ static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, - mips_instruction); + mips_insn); static int fpux_emu(struct pt_regs *, - struct mips_fpu_struct *, mips_instruction, void __user **); + struct mips_fpu_struct *, mips_insn, void __user **); /* Control registers */ @@ -846,7 +846,7 @@ do { \ * Emulate a CFC1 instruction. */ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { u32 fcr31 = ctx->fcr31; u32 value = 0; @@ -903,7 +903,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Emulate a CTC1 instruction. */ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { u32 fcr31 = ctx->fcr31; u32 value; @@ -973,7 +973,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, { unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned int cond, cbit, bit0; - mips_instruction ir; + mips_insn ir; int likely, pc_inc; union fpureg *fpr; u32 __user *wva; @@ -1461,7 +1461,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir, void __user **fault_addr) + mips_insn ir, void __user **fault_addr) { unsigned int rcsr = 0; /* resulting csr */ @@ -1680,7 +1680,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Emulate a single COP1 arithmetic instruction. */ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { int rfmt; /* resulting format */ unsigned int rcsr = 0; /* resulting csr */ @@ -2899,9 +2899,9 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, dec_insn.micro_mips_mode = 1; } else { if ((get_user(dec_insn.insn, - (mips_instruction __user *) xcp->cp0_epc)) || + (mips_insn __user *) xcp->cp0_epc)) || (get_user(dec_insn.next_insn, - (mips_instruction __user *)(xcp->cp0_epc+4)))) { + (mips_insn __user *)(xcp->cp0_epc+4)))) { MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index e02bd20b60a6..d4ea2cf89006 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -61,8 +61,8 @@ * couldn't already. */ struct emuframe { - mips_instruction emul; - mips_instruction badinst; + mips_insn emul; + mips_insn badinst; }; static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe); @@ -206,11 +206,11 @@ void dsemul_mm_cleanup(struct mm_struct *mm) bitmap_free(mm_ctx->bd_emupage_allocmap); } -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, +int mips_dsemul(struct pt_regs *regs, mips_insn ir, unsigned long branch_pc, unsigned long cont_pc) { int isa16 = get_isa16_mode(regs->cp0_epc); - mips_instruction break_math; + mips_insn break_math; unsigned long fr_uaddr; struct emuframe fr; int fr_idx, ret;