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Fri, 17 Aug 2018 05:25:05 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fqdoK-0000U3-Ik; Fri, 17 Aug 2018 05:25:00 -0700 Received: from xsj-pvapsmtp01 (xsj-mail.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w7HCOwFQ019101; Fri, 17 Aug 2018 05:24:58 -0700 Received: from [172.23.64.8] (helo=xhdvnc108.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fqdoI-0000Tf-FP; Fri, 17 Aug 2018 05:24:58 -0700 Received: by xhdvnc108.xilinx.com (Postfix, from userid 15427) id 802B96050E; Fri, 17 Aug 2018 17:54:57 +0530 (IST) From: Anurag Kumar Vulisha To: , CC: , , , Anurag Kumar Vulisha Subject: [PATCH v2 7/8] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields Date: Fri, 17 Aug 2018 17:54:54 +0530 Message-ID: <1534508695-12642-8-git-send-email-anurag.kumar.vulisha@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1534508695-12642-1-git-send-email-anurag.kumar.vulisha@xilinx.com> References: <1534508695-12642-1-git-send-email-anurag.kumar.vulisha@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39850400004)(136003)(346002)(376002)(396003)(2980300002)(438002)(189003)(199004)(8676002)(47776003)(90966002)(81166006)(81156014)(6666003)(5660300001)(478600001)(52956003)(2906002)(336012)(486006)(446003)(316002)(26005)(42186006)(11346002)(16586007)(106002)(36386004)(63266004)(8936002)(48376002)(76176011)(426003)(36756003)(51416003)(103686004)(356003)(186003)(4326008)(107886003)(6266002)(39060400002)(2616005)(110136005)(54906003)(106466001)(305945005)(126002)(50226002)(14444005)(50466002)(476003)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY4PR0201MB3506;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; 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This logic doesn't work if multiple TRBs are queued per request and the IOC/LST bit is set on the last TRB of that request. Consider an example where a queued request has multiple queued TRBs and IOC/LST bit is set only for the last TRB. In this case, the Core generates XferComplete/XferInProgress events only for the last TRB (since IOC/LST are set only for the last TRB). As per the logic in dwc3_gadget_ep_reclaim_completed_trb() event->status is checked for IOC/LST bit and returns on the first TRB. This makes the remaining TRBs left unhandled. To aviod this, changed the code to check for IOC/LST bits in both event->status & TRB->ctrl. This patch does the same. Signed-off-by: Anurag Kumar Vulisha --- Changes in v2: 1. None --- drivers/usb/dwc3/gadget.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 3af55f8..1b1bc14 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2290,7 +2290,12 @@ static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, if (event->status & DEPEVT_STATUS_SHORT && !chain) return 1; - if (event->status & (DEPEVT_STATUS_IOC | DEPEVT_STATUS_LST)) + if ((event->status & DEPEVT_STATUS_IOC) && + (trb->ctrl & DWC3_TRB_CTRL_IOC)) + return 1; + + if ((event->status & DEPEVT_STATUS_LST) && + (trb->ctrl & DWC3_TRB_CTRL_LST)) return 1; return 0;